1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com> 4 */ 5 6 #include <common.h> 7 #include <netdev.h> 8 #include <asm/arch/cpu.h> 9 #include <asm/arch/clk.h> 10 #include <asm/arch/wdt.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/io.h> 13 14 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; 15 static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; 16 17 void reset_cpu(ulong addr) 18 { 19 /* Enable watchdog clock */ 20 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); 21 22 /* To be compatible with the original U-Boot code: 23 * addr: - 0: perform hard reset. 24 * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */ 25 if (addr == 0) { 26 /* Reset pulse length is 13005 peripheral clock frames */ 27 writel(13000, &wdt->pulse); 28 29 /* Force WDOG_RESET2 and RESOUT_N signal active */ 30 writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 31 | WDTIM_MCTRL_M_RES2, &wdt->mctrl); 32 } else { 33 /* Force match output active */ 34 writel(0x01, &wdt->emr); 35 36 /* Internal reset on match output (no pulse on "RESOUT_N") */ 37 writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); 38 } 39 40 while (1) 41 /* NOP */; 42 } 43 44 #if defined(CONFIG_ARCH_CPU_INIT) 45 int arch_cpu_init(void) 46 { 47 /* 48 * It might be necessary to flush data cache, if U-Boot is loaded 49 * from kickstart bootloader, e.g. from S1L loader 50 */ 51 flush_dcache_all(); 52 53 return 0; 54 } 55 #else 56 #error "You have to select CONFIG_ARCH_CPU_INIT" 57 #endif 58 59 #if defined(CONFIG_DISPLAY_CPUINFO) 60 int print_cpuinfo(void) 61 { 62 printf("CPU: NXP LPC32XX\n"); 63 printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000); 64 printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000); 65 printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000); 66 67 return 0; 68 } 69 #endif 70 71 #ifdef CONFIG_LPC32XX_ETH 72 int cpu_eth_init(bd_t *bis) 73 { 74 lpc32xx_eth_initialize(bis); 75 return 0; 76 } 77 #endif 78