xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c (revision 3f82d89d)
1 /*
2  * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17  * MA 02110-1301, USA.
18  */
19 
20 #include <common.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/clk.h>
23 #include <asm/arch/wdt.h>
24 #include <asm/io.h>
25 
26 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
27 static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
28 
29 void reset_cpu(ulong addr)
30 {
31 	/* Enable watchdog clock */
32 	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
33 
34 	/* Reset pulse length is 13005 peripheral clock frames */
35 	writel(13000, &wdt->pulse);
36 
37 	/* Force WDOG_RESET2 and RESOUT_N signal active */
38 	writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
39 	       &wdt->mctrl);
40 
41 	while (1)
42 		/* NOP */;
43 }
44 
45 #if defined(CONFIG_ARCH_CPU_INIT)
46 int arch_cpu_init(void)
47 {
48 	/*
49 	 * It might be necessary to flush data cache, if U-boot is loaded
50 	 * from kickstart bootloader, e.g. from S1L loader
51 	 */
52 	flush_dcache_all();
53 
54 	return 0;
55 }
56 #else
57 #error "You have to select CONFIG_ARCH_CPU_INIT"
58 #endif
59 
60 #if defined(CONFIG_DISPLAY_CPUINFO)
61 int print_cpuinfo(void)
62 {
63 	printf("CPU:   NXP LPC32XX\n");
64 	printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
65 	printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
66 	printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
67 
68 	return 0;
69 }
70 #endif
71