1 /* 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/clk.h> 11 #include <asm/arch/wdt.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/io.h> 14 15 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; 16 static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; 17 18 void reset_cpu(ulong addr) 19 { 20 /* Enable watchdog clock */ 21 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); 22 23 /* Reset pulse length is 13005 peripheral clock frames */ 24 writel(13000, &wdt->pulse); 25 26 /* Force WDOG_RESET2 and RESOUT_N signal active */ 27 writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, 28 &wdt->mctrl); 29 30 while (1) 31 /* NOP */; 32 } 33 34 #if defined(CONFIG_ARCH_CPU_INIT) 35 int arch_cpu_init(void) 36 { 37 /* 38 * It might be necessary to flush data cache, if U-boot is loaded 39 * from kickstart bootloader, e.g. from S1L loader 40 */ 41 flush_dcache_all(); 42 43 return 0; 44 } 45 #else 46 #error "You have to select CONFIG_ARCH_CPU_INIT" 47 #endif 48 49 #if defined(CONFIG_DISPLAY_CPUINFO) 50 int print_cpuinfo(void) 51 { 52 printf("CPU: NXP LPC32XX\n"); 53 printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000); 54 printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000); 55 printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000); 56 57 return 0; 58 } 59 #endif 60 61 #ifdef CONFIG_LPC32XX_ETH 62 int cpu_eth_init(bd_t *bis) 63 { 64 lpc32xx_eth_initialize(bis); 65 return 0; 66 } 67 #endif 68