xref: /openbmc/u-boot/arch/arm/cpu/arm926ejs/cache.c (revision ca6c5e03)
1 /*
2  * (C) Copyright 2011
3  * Ilya Yanok, EmCraft Systems
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 #include <linux/types.h>
8 #include <common.h>
9 
10 #ifndef CONFIG_SYS_DCACHE_OFF
11 
12 #ifndef CONFIG_SYS_CACHELINE_SIZE
13 #define CONFIG_SYS_CACHELINE_SIZE	32
14 #endif
15 
16 void invalidate_dcache_all(void)
17 {
18 	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
19 }
20 
21 void flush_dcache_all(void)
22 {
23 	asm volatile(
24 		"0:"
25 		"mrc p15, 0, r15, c7, c14, 3\n"
26 		"bne 0b\n"
27 		"mcr p15, 0, %0, c7, c10, 4\n"
28 		 : : "r"(0) : "memory"
29 	);
30 }
31 
32 void invalidate_dcache_range(unsigned long start, unsigned long stop)
33 {
34 	if (!check_cache_range(start, stop))
35 		return;
36 
37 	while (start < stop) {
38 		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
39 		start += CONFIG_SYS_CACHELINE_SIZE;
40 	}
41 }
42 
43 void flush_dcache_range(unsigned long start, unsigned long stop)
44 {
45 	if (!check_cache_range(start, stop))
46 		return;
47 
48 	while (start < stop) {
49 		asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
50 		start += CONFIG_SYS_CACHELINE_SIZE;
51 	}
52 
53 	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
54 }
55 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
56 void invalidate_dcache_all(void)
57 {
58 }
59 
60 void flush_dcache_all(void)
61 {
62 }
63 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
64 
65 /*
66  * Stub implementations for l2 cache operations
67  */
68 
69 __weak void l2_cache_disable(void) {}
70 
71 #if defined CONFIG_SYS_THUMB_BUILD
72 __weak void invalidate_l2_cache(void) {}
73 #endif
74