1 /* 2 * (C) Copyright 2010 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * Contributor: Mahavir Jain <mjain@marvell.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23 * MA 02110-1301 USA 24 */ 25 26 #include <common.h> 27 #include <asm/arch/armada100.h> 28 29 /* 30 * Timer registers 31 * Refer Section A.6 in Datasheet 32 */ 33 struct armd1tmr_registers { 34 u32 clk_ctrl; /* Timer clk control reg */ 35 u32 match[9]; /* Timer match registers */ 36 u32 count[3]; /* Timer count registers */ 37 u32 status[3]; 38 u32 ie[3]; 39 u32 preload[3]; /* Timer preload value */ 40 u32 preload_ctrl[3]; 41 u32 wdt_match_en; 42 u32 wdt_match_r; 43 u32 wdt_val; 44 u32 wdt_sts; 45 u32 icr[3]; 46 u32 wdt_icr; 47 u32 cer; /* Timer count enable reg */ 48 u32 cmr; 49 u32 ilr[3]; 50 u32 wcr; 51 u32 wfar; 52 u32 wsar; 53 u32 cvwr; 54 }; 55 56 #define TIMER 0 /* Use TIMER 0 */ 57 /* Each timer has 3 match registers */ 58 #define MATCH_CMP(x) ((3 * TIMER) + x) 59 #define TIMER_LOAD_VAL 0xffffffff 60 #define COUNT_RD_REQ 0x1 61 62 DECLARE_GLOBAL_DATA_PTR; 63 /* Using gd->tbu from timestamp and gd->tbl for lastdec */ 64 65 /* For preventing risk of instability in reading counter value, 66 * first set read request to register cvwr and then read same 67 * register after it captures counter value. 68 */ 69 ulong read_timer(void) 70 { 71 struct armd1tmr_registers *armd1timers = 72 (struct armd1tmr_registers *) ARMD1_TIMER_BASE; 73 volatile int loop=100; 74 75 writel(COUNT_RD_REQ, &armd1timers->cvwr); 76 while (loop--); 77 return(readl(&armd1timers->cvwr)); 78 } 79 80 void reset_timer_masked(void) 81 { 82 /* reset time */ 83 gd->tbl = read_timer(); 84 gd->tbu = 0; 85 } 86 87 ulong get_timer_masked(void) 88 { 89 ulong now = read_timer(); 90 91 if (now >= gd->tbl) { 92 /* normal mode */ 93 gd->tbu += now - gd->tbl; 94 } else { 95 /* we have an overflow ... */ 96 gd->tbu += now + TIMER_LOAD_VAL - gd->tbl; 97 } 98 gd->tbl = now; 99 100 return gd->tbu; 101 } 102 103 void reset_timer(void) 104 { 105 reset_timer_masked(); 106 } 107 108 ulong get_timer(ulong base) 109 { 110 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - 111 base); 112 } 113 114 void set_timer(ulong t) 115 { 116 gd->tbu = t; 117 } 118 119 void __udelay(unsigned long usec) 120 { 121 ulong delayticks; 122 ulong endtime; 123 124 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); 125 endtime = get_timer_masked() + delayticks; 126 127 while (get_timer_masked() < endtime); 128 } 129 130 /* 131 * init the Timer 132 */ 133 int timer_init(void) 134 { 135 struct armd1apb1_registers *apb1clkres = 136 (struct armd1apb1_registers *) ARMD1_APBC1_BASE; 137 struct armd1tmr_registers *armd1timers = 138 (struct armd1tmr_registers *) ARMD1_TIMER_BASE; 139 140 /* Enable Timer clock at 3.25 MHZ */ 141 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); 142 143 /* load value into timer */ 144 writel(0x0, &armd1timers->clk_ctrl); 145 /* Use Timer 0 Match Resiger 0 */ 146 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]); 147 /* Preload value is 0 */ 148 writel(0x0, &armd1timers->preload[TIMER]); 149 /* Enable match comparator 0 for Timer 0 */ 150 writel(0x1, &armd1timers->preload_ctrl[TIMER]); 151 152 /* Enable timer 0 */ 153 writel(0x1, &armd1timers->cer); 154 /* init the gd->tbu and gd->tbl value */ 155 reset_timer_masked(); 156 157 return 0; 158 } 159 160 #define MPMU_APRR_WDTR (1<<4) 161 #define TMR_WFAR 0xbaba /* WDT Register First key */ 162 #define TMP_WSAR 0xeb10 /* WDT Register Second key */ 163 164 /* 165 * This function uses internal Watchdog Timer 166 * based reset mechanism. 167 * Steps to write watchdog registers (protected access) 168 * 1. Write key value to TMR_WFAR reg. 169 * 2. Write key value to TMP_WSAR reg. 170 * 3. Perform write operation. 171 */ 172 void reset_cpu (unsigned long ignored) 173 { 174 struct armd1mpmu_registers *mpmu = 175 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; 176 struct armd1tmr_registers *armd1timers = 177 (struct armd1tmr_registers *) ARMD1_TIMER_BASE; 178 u32 val; 179 180 /* negate hardware reset to the WDT after system reset */ 181 val = readl(&mpmu->aprr); 182 val = val | MPMU_APRR_WDTR; 183 writel(val, &mpmu->aprr); 184 185 /* reset/enable WDT clock */ 186 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr); 187 readl(&mpmu->wdtpcr); 188 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); 189 readl(&mpmu->wdtpcr); 190 191 /* clear previous WDT status */ 192 writel(TMR_WFAR, &armd1timers->wfar); 193 writel(TMP_WSAR, &armd1timers->wsar); 194 writel(0, &armd1timers->wdt_sts); 195 196 /* set match counter */ 197 writel(TMR_WFAR, &armd1timers->wfar); 198 writel(TMP_WSAR, &armd1timers->wsar); 199 writel(0xf, &armd1timers->wdt_match_r); 200 201 /* enable WDT reset */ 202 writel(TMR_WFAR, &armd1timers->wfar); 203 writel(TMP_WSAR, &armd1timers->wsar); 204 writel(0x3, &armd1timers->wdt_match_en); 205 206 while(1); 207 } 208