1 /*
2  * (C) Copyright 2010
3  * Marvell Semiconductor <www.marvell.com>
4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5  * Contributor: Mahavir Jain <mjain@marvell.com>
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23  * MA 02110-1301 USA
24  */
25 
26 #include <common.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/armada100.h>
29 
30 #define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
31 #define SET_MRVL_ID	(1<<8)
32 #define L2C_RAM_SEL	(1<<4)
33 
34 int arch_cpu_init(void)
35 {
36 	u32 val;
37 	struct armd1cpu_registers *cpuregs =
38 		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
39 
40 	struct armd1apb1_registers *apb1clkres =
41 		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
42 
43 	struct armd1mpmu_registers *mpmu =
44 		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
45 
46 	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
47 	val = readl(&cpuregs->cpu_conf);
48 	val = val | SET_MRVL_ID;
49 	writel(val, &cpuregs->cpu_conf);
50 
51 	/* Enable Clocks for all hardware units */
52 	writel(0xFFFFFFFF, &mpmu->acgr);
53 
54 	/* Turn on AIB and AIB-APB Functional clock */
55 	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
56 
57 	/* ensure L2 cache is not mapped as SRAM */
58 	val = readl(&cpuregs->cpu_conf);
59 	val = val & ~(L2C_RAM_SEL);
60 	writel(val, &cpuregs->cpu_conf);
61 
62 	/* Enable GPIO clock */
63 	writel(APBC_APBCLK, &apb1clkres->gpio);
64 
65 #ifdef CONFIG_I2C_MV
66 	/* Enable general I2C clock */
67 	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
68 	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
69 
70 	/* Enable power I2C clock */
71 	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
72 	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
73 #endif
74 
75 	/*
76 	 * Enable Functional and APB clock at 14.7456MHz
77 	 * for configured UART console
78 	 */
79 #if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
80 	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
81 #elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
82 	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
83 #else
84 	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
85 #endif
86 	icache_enable();
87 
88 	return 0;
89 }
90 
91 #if defined(CONFIG_DISPLAY_CPUINFO)
92 int print_cpuinfo(void)
93 {
94 	u32 id;
95 	struct armd1cpu_registers *cpuregs =
96 		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
97 
98 	id = readl(&cpuregs->chip_id);
99 	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
100 	return 0;
101 }
102 #endif
103 
104 #ifdef CONFIG_I2C_MV
105 void i2c_clk_enable(void)
106 {
107 }
108 #endif
109