xref: /openbmc/u-boot/arch/arm/cpu/arm920t/start.S (revision ee52b188) 
1/*
2 *  armboot - Startup Code for ARM920 CPU-core
3 *
4 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
5 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
6 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <asm-offsets.h>
28#include <common.h>
29#include <config.h>
30
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
41_start:	b	start_code
42	ldr	pc, _undefined_instruction
43	ldr	pc, _software_interrupt
44	ldr	pc, _prefetch_abort
45	ldr	pc, _data_abort
46	ldr	pc, _not_used
47	ldr	pc, _irq
48	ldr	pc, _fiq
49
50_undefined_instruction:	.word undefined_instruction
51_software_interrupt:	.word software_interrupt
52_prefetch_abort:	.word prefetch_abort
53_data_abort:		.word data_abort
54_not_used:		.word not_used
55_irq:			.word irq
56_fiq:			.word fiq
57
58	.balignl 16,0xdeadbeef
59
60
61/*
62 *************************************************************************
63 *
64 * Startup Code (called from the ARM reset exception vector)
65 *
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
68 * setup stack
69 * jump to second stage
70 *
71 *************************************************************************
72 */
73
74.globl _TEXT_BASE
75_TEXT_BASE:
76	.word	CONFIG_SYS_TEXT_BASE
77
78/*
79 * These are defined in the board-specific linker script.
80 * Subtracting _start from them lets the linker put their
81 * relative position in the executable instead of leaving
82 * them null.
83 */
84.globl _bss_start_ofs
85_bss_start_ofs:
86	.word __bss_start - _start
87
88.globl _bss_end_ofs
89_bss_end_ofs:
90	.word __bss_end__ - _start
91
92.globl _end_ofs
93_end_ofs:
94	.word _end - _start
95
96#ifdef CONFIG_USE_IRQ
97/* IRQ stack memory (calculated at run-time) */
98.globl IRQ_STACK_START
99IRQ_STACK_START:
100	.word	0x0badc0de
101
102/* IRQ stack memory (calculated at run-time) */
103.globl FIQ_STACK_START
104FIQ_STACK_START:
105	.word 0x0badc0de
106#endif
107
108/* IRQ stack memory (calculated at run-time) + 8 bytes */
109.globl IRQ_STACK_START_IN
110IRQ_STACK_START_IN:
111	.word	0x0badc0de
112
113/*
114 * the actual start code
115 */
116
117start_code:
118	/*
119	 * set the cpu to SVC32 mode
120	 */
121	mrs	r0, cpsr
122	bic	r0, r0, #0x1f
123	orr	r0, r0, #0xd3
124	msr	cpsr, r0
125
126#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
127	/*
128	 * relocate exception table
129	 */
130	ldr	r0, =_start
131	ldr	r1, =0x0
132	mov	r2, #16
133copyex:
134	subs	r2, r2, #1
135	ldr	r3, [r0], #4
136	str	r3, [r1], #4
137	bne	copyex
138#endif
139
140#ifdef CONFIG_S3C24X0
141	/* turn off the watchdog */
142
143# if defined(CONFIG_S3C2400)
144#  define pWTCON	0x15300000
145#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
146#  define CLKDIVN	0x14800014	/* clock divisor register */
147#else
148#  define pWTCON	0x53000000
149#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
150#  define INTSUBMSK	0x4A00001C
151#  define CLKDIVN	0x4C000014	/* clock divisor register */
152# endif
153
154	ldr	r0, =pWTCON
155	mov	r1, #0x0
156	str	r1, [r0]
157
158	/*
159	 * mask all IRQs by setting all bits in the INTMR - default
160	 */
161	mov	r1, #0xffffffff
162	ldr	r0, =INTMSK
163	str	r1, [r0]
164# if defined(CONFIG_S3C2410)
165	ldr	r1, =0x3ff
166	ldr	r0, =INTSUBMSK
167	str	r1, [r0]
168# endif
169
170	/* FCLK:HCLK:PCLK = 1:2:4 */
171	/* default FCLK is 120 MHz ! */
172	ldr	r0, =CLKDIVN
173	mov	r1, #3
174	str	r1, [r0]
175#endif	/* CONFIG_S3C24X0 */
176
177	/*
178	 * we do sys-critical inits only at reboot,
179	 * not when booting from ram!
180	 */
181#ifndef CONFIG_SKIP_LOWLEVEL_INIT
182	bl	cpu_init_crit
183#endif
184
185/* Set stackpointer in internal RAM to call board_init_f */
186call_board_init_f:
187	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
188	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
189	ldr	r0,=0x00000000
190	bl	board_init_f
191
192/*------------------------------------------------------------------------------*/
193
194/*
195 * void relocate_code (addr_sp, gd, addr_moni)
196 *
197 * This "function" does not return, instead it continues in RAM
198 * after relocating the monitor code.
199 *
200 */
201	.globl	relocate_code
202relocate_code:
203	mov	r4, r0	/* save addr_sp */
204	mov	r5, r1	/* save addr of gd */
205	mov	r6, r2	/* save addr of destination */
206
207	/* Set up the stack						    */
208stack_setup:
209	mov	sp, r4
210
211	adr	r0, _start
212	cmp	r0, r6
213	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
214	beq	clear_bss		/* skip relocation */
215	mov	r1, r6			/* r1 <- scratch for copy_loop */
216	ldr	r3, _bss_start_ofs
217	add	r2, r0, r3		/* r2 <- source end address	    */
218
219copy_loop:
220	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
221	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
222	cmp	r0, r2			/* until source end address [r2]    */
223	blo	copy_loop
224
225#ifndef CONFIG_SPL_BUILD
226	/*
227	 * fix .rel.dyn relocations
228	 */
229	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
230	sub	r9, r6, r0		/* r9 <- relocation offset */
231	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
232	add	r10, r10, r0		/* r10 <- sym table in FLASH */
233	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
234	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
235	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
236	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
237fixloop:
238	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
239	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
240	ldr	r1, [r2, #4]
241	and	r7, r1, #0xff
242	cmp	r7, #23			/* relative fixup? */
243	beq	fixrel
244	cmp	r7, #2			/* absolute fixup? */
245	beq	fixabs
246	/* ignore unknown type of fixup */
247	b	fixnext
248fixabs:
249	/* absolute fix: set location to (offset) symbol value */
250	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
251	add	r1, r10, r1		/* r1 <- address of symbol in table */
252	ldr	r1, [r1, #4]		/* r1 <- symbol value */
253	add	r1, r1, r9		/* r1 <- relocated sym addr */
254	b	fixnext
255fixrel:
256	/* relative fix: increase location by offset */
257	ldr	r1, [r0]
258	add	r1, r1, r9
259fixnext:
260	str	r1, [r0]
261	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
262	cmp	r2, r3
263	blo	fixloop
264#endif
265
266clear_bss:
267#ifndef CONFIG_SPL_BUILD
268	ldr	r0, _bss_start_ofs
269	ldr	r1, _bss_end_ofs
270	mov	r4, r6			/* reloc addr */
271	add	r0, r0, r4
272	add	r1, r1, r4
273	mov	r2, #0x00000000		/* clear			    */
274
275clbss_l:cmp	r0, r1			/* clear loop... */
276	bhs	clbss_e			/* if reached end of bss, exit */
277	str	r2, [r0]
278	add	r0, r0, #4
279	b	clbss_l
280clbss_e:
281
282	bl coloured_LED_init
283	bl red_led_on
284#endif
285
286/*
287 * We are done. Do not return, instead branch to second part of board
288 * initialization, now running from RAM.
289 */
290#ifdef CONFIG_NAND_SPL
291	ldr     r0, _nand_boot_ofs
292	mov	pc, r0
293
294_nand_boot_ofs:
295	.word nand_boot
296#else
297	ldr	r0, _board_init_r_ofs
298	adr	r1, _start
299	add	lr, r0, r1
300	add	lr, lr, r9
301	/* setup parameters for board_init_r */
302	mov	r0, r5		/* gd_t */
303	mov	r1, r6		/* dest_addr */
304	/* jump to it ... */
305	mov	pc, lr
306
307_board_init_r_ofs:
308	.word board_init_r - _start
309#endif
310
311_rel_dyn_start_ofs:
312	.word __rel_dyn_start - _start
313_rel_dyn_end_ofs:
314	.word __rel_dyn_end - _start
315_dynsym_start_ofs:
316	.word __dynsym_start - _start
317
318/*
319 *************************************************************************
320 *
321 * CPU_init_critical registers
322 *
323 * setup important registers
324 * setup memory timing
325 *
326 *************************************************************************
327 */
328
329
330#ifndef CONFIG_SKIP_LOWLEVEL_INIT
331cpu_init_crit:
332	/*
333	 * flush v4 I/D caches
334	 */
335	mov	r0, #0
336	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
337	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
338
339	/*
340	 * disable MMU stuff and caches
341	 */
342	mrc	p15, 0, r0, c1, c0, 0
343	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
344	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
345	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
346	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
347	mcr	p15, 0, r0, c1, c0, 0
348
349	/*
350	 * before relocating, we have to setup RAM timing
351	 * because memory timing is board-dependend, you will
352	 * find a lowlevel_init.S in your board directory.
353	 */
354	mov	ip, lr
355
356	bl	lowlevel_init
357
358	mov	lr, ip
359	mov	pc, lr
360#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
361
362/*
363 *************************************************************************
364 *
365 * Interrupt handling
366 *
367 *************************************************************************
368 */
369
370@
371@ IRQ stack frame.
372@
373#define S_FRAME_SIZE	72
374
375#define S_OLD_R0	68
376#define S_PSR		64
377#define S_PC		60
378#define S_LR		56
379#define S_SP		52
380
381#define S_IP		48
382#define S_FP		44
383#define S_R10		40
384#define S_R9		36
385#define S_R8		32
386#define S_R7		28
387#define S_R6		24
388#define S_R5		20
389#define S_R4		16
390#define S_R3		12
391#define S_R2		8
392#define S_R1		4
393#define S_R0		0
394
395#define MODE_SVC	0x13
396#define I_BIT		0x80
397
398/*
399 * use bad_save_user_regs for abort/prefetch/undef/swi ...
400 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
401 */
402
403	.macro	bad_save_user_regs
404	sub	sp, sp, #S_FRAME_SIZE
405	stmia	sp, {r0 - r12}			@ Calling r0-r12
406	ldr	r2, IRQ_STACK_START_IN
407	ldmia	r2, {r2 - r3}			@ get pc, cpsr
408	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
409
410	add	r5, sp, #S_SP
411	mov	r1, lr
412	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
413	mov	r0, sp
414	.endm
415
416	.macro	irq_save_user_regs
417	sub	sp, sp, #S_FRAME_SIZE
418	stmia	sp, {r0 - r12}			@ Calling r0-r12
419	add	r7, sp, #S_PC
420	stmdb	r7, {sp, lr}^			@ Calling SP, LR
421	str	lr, [r7, #0]			@ Save calling PC
422	mrs	r6, spsr
423	str	r6, [r7, #4]			@ Save CPSR
424	str	r0, [r7, #8]			@ Save OLD_R0
425	mov	r0, sp
426	.endm
427
428	.macro	irq_restore_user_regs
429	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
430	mov	r0, r0
431	ldr	lr, [sp, #S_PC]			@ Get PC
432	add	sp, sp, #S_FRAME_SIZE
433	/* return & move spsr_svc into cpsr */
434	subs	pc, lr, #4
435	.endm
436
437	.macro get_bad_stack
438	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
439
440	str	lr, [r13]			@ save caller lr / spsr
441	mrs	lr, spsr
442	str	lr, [r13, #4]
443
444	mov	r13, #MODE_SVC			@ prepare SVC-Mode
445	@ msr	spsr_c, r13
446	msr	spsr, r13
447	mov	lr, pc
448	movs	pc, lr
449	.endm
450
451	.macro get_irq_stack			@ setup IRQ stack
452	ldr	sp, IRQ_STACK_START
453	.endm
454
455	.macro get_fiq_stack			@ setup FIQ stack
456	ldr	sp, FIQ_STACK_START
457	.endm
458
459/*
460 * exception handlers
461 */
462	.align  5
463undefined_instruction:
464	get_bad_stack
465	bad_save_user_regs
466	bl	do_undefined_instruction
467
468	.align	5
469software_interrupt:
470	get_bad_stack
471	bad_save_user_regs
472	bl	do_software_interrupt
473
474	.align	5
475prefetch_abort:
476	get_bad_stack
477	bad_save_user_regs
478	bl	do_prefetch_abort
479
480	.align	5
481data_abort:
482	get_bad_stack
483	bad_save_user_regs
484	bl	do_data_abort
485
486	.align	5
487not_used:
488	get_bad_stack
489	bad_save_user_regs
490	bl	do_not_used
491
492#ifdef CONFIG_USE_IRQ
493
494	.align	5
495irq:
496	get_irq_stack
497	irq_save_user_regs
498	bl	do_irq
499	irq_restore_user_regs
500
501	.align	5
502fiq:
503	get_fiq_stack
504	/* someone ought to write a more effiction fiq_save_user_regs */
505	irq_save_user_regs
506	bl	do_fiq
507	irq_restore_user_regs
508
509#else
510
511	.align	5
512irq:
513	get_bad_stack
514	bad_save_user_regs
515	bl	do_irq
516
517	.align	5
518fiq:
519	get_bad_stack
520	bad_save_user_regs
521	bl	do_fiq
522
523#endif
524