xref: /openbmc/u-boot/arch/arm/cpu/arm920t/start.S (revision b1e6c4c3) 
1/*
2 *  armboot - Startup Code for ARM920 CPU-core
3 *
4 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
5 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
6 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <asm-offsets.h>
28#include <common.h>
29#include <config.h>
30
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
41_start:	b	start_code
42	ldr	pc, _undefined_instruction
43	ldr	pc, _software_interrupt
44	ldr	pc, _prefetch_abort
45	ldr	pc, _data_abort
46	ldr	pc, _not_used
47	ldr	pc, _irq
48	ldr	pc, _fiq
49
50_undefined_instruction:	.word undefined_instruction
51_software_interrupt:	.word software_interrupt
52_prefetch_abort:	.word prefetch_abort
53_data_abort:		.word data_abort
54_not_used:		.word not_used
55_irq:			.word irq
56_fiq:			.word fiq
57
58	.balignl 16,0xdeadbeef
59
60
61/*
62 *************************************************************************
63 *
64 * Startup Code (called from the ARM reset exception vector)
65 *
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
68 * setup stack
69 * jump to second stage
70 *
71 *************************************************************************
72 */
73
74.globl _TEXT_BASE
75_TEXT_BASE:
76#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
77	.word	CONFIG_SPL_TEXT_BASE
78#else
79	.word	CONFIG_SYS_TEXT_BASE
80#endif
81
82/*
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
86 * them null.
87 */
88.globl _bss_start_ofs
89_bss_start_ofs:
90	.word __bss_start - _start
91
92.globl _image_copy_end_ofs
93_image_copy_end_ofs:
94	.word __image_copy_end - _start
95
96.globl _bss_end_ofs
97_bss_end_ofs:
98	.word __bss_end - _start
99
100.globl _end_ofs
101_end_ofs:
102	.word _end - _start
103
104#ifdef CONFIG_USE_IRQ
105/* IRQ stack memory (calculated at run-time) */
106.globl IRQ_STACK_START
107IRQ_STACK_START:
108	.word	0x0badc0de
109
110/* IRQ stack memory (calculated at run-time) */
111.globl FIQ_STACK_START
112FIQ_STACK_START:
113	.word 0x0badc0de
114#endif
115
116/* IRQ stack memory (calculated at run-time) + 8 bytes */
117.globl IRQ_STACK_START_IN
118IRQ_STACK_START_IN:
119	.word	0x0badc0de
120
121/*
122 * the actual start code
123 */
124
125start_code:
126	/*
127	 * set the cpu to SVC32 mode
128	 */
129	mrs	r0, cpsr
130	bic	r0, r0, #0x1f
131	orr	r0, r0, #0xd3
132	msr	cpsr, r0
133
134#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
135	/*
136	 * relocate exception table
137	 */
138	ldr	r0, =_start
139	ldr	r1, =0x0
140	mov	r2, #16
141copyex:
142	subs	r2, r2, #1
143	ldr	r3, [r0], #4
144	str	r3, [r1], #4
145	bne	copyex
146#endif
147
148#ifdef CONFIG_S3C24X0
149	/* turn off the watchdog */
150
151# if defined(CONFIG_S3C2400)
152#  define pWTCON	0x15300000
153#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
154#  define CLKDIVN	0x14800014	/* clock divisor register */
155#else
156#  define pWTCON	0x53000000
157#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
158#  define INTSUBMSK	0x4A00001C
159#  define CLKDIVN	0x4C000014	/* clock divisor register */
160# endif
161
162	ldr	r0, =pWTCON
163	mov	r1, #0x0
164	str	r1, [r0]
165
166	/*
167	 * mask all IRQs by setting all bits in the INTMR - default
168	 */
169	mov	r1, #0xffffffff
170	ldr	r0, =INTMSK
171	str	r1, [r0]
172# if defined(CONFIG_S3C2410)
173	ldr	r1, =0x3ff
174	ldr	r0, =INTSUBMSK
175	str	r1, [r0]
176# endif
177
178	/* FCLK:HCLK:PCLK = 1:2:4 */
179	/* default FCLK is 120 MHz ! */
180	ldr	r0, =CLKDIVN
181	mov	r1, #3
182	str	r1, [r0]
183#endif	/* CONFIG_S3C24X0 */
184
185	/*
186	 * we do sys-critical inits only at reboot,
187	 * not when booting from ram!
188	 */
189#ifndef CONFIG_SKIP_LOWLEVEL_INIT
190	bl	cpu_init_crit
191#endif
192
193	bl	_main
194
195/*------------------------------------------------------------------------------*/
196
197/*
198 * void relocate_code(addr_moni)
199 *
200 * This function relocates the monitor code.
201 */
202	.globl	relocate_code
203relocate_code:
204	mov	r6, r0	/* save addr of destination */
205
206	adr	r0, _start
207	subs	r9, r6, r0		/* r9 <- relocation offset */
208	beq	relocate_done		/* skip relocation */
209	mov	r1, r6			/* r1 <- scratch for copy_loop */
210	ldr	r3, _image_copy_end_ofs
211	add	r2, r0, r3		/* r2 <- source end address	    */
212
213copy_loop:
214	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
215	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
216	cmp	r0, r2			/* until source end address [r2]    */
217	blo	copy_loop
218
219#ifndef CONFIG_SPL_BUILD
220	/*
221	 * fix .rel.dyn relocations
222	 */
223	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
224	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
225	add	r10, r10, r0		/* r10 <- sym table in FLASH */
226	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
227	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
228	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
229	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
230fixloop:
231	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
232	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
233	ldr	r1, [r2, #4]
234	and	r7, r1, #0xff
235	cmp	r7, #23			/* relative fixup? */
236	beq	fixrel
237	cmp	r7, #2			/* absolute fixup? */
238	beq	fixabs
239	/* ignore unknown type of fixup */
240	b	fixnext
241fixabs:
242	/* absolute fix: set location to (offset) symbol value */
243	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
244	add	r1, r10, r1		/* r1 <- address of symbol in table */
245	ldr	r1, [r1, #4]		/* r1 <- symbol value */
246	add	r1, r1, r9		/* r1 <- relocated sym addr */
247	b	fixnext
248fixrel:
249	/* relative fix: increase location by offset */
250	ldr	r1, [r0]
251	add	r1, r1, r9
252fixnext:
253	str	r1, [r0]
254	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
255	cmp	r2, r3
256	blo	fixloop
257#endif
258
259relocate_done:
260
261	mov	pc, lr
262
263_rel_dyn_start_ofs:
264	.word __rel_dyn_start - _start
265_rel_dyn_end_ofs:
266	.word __rel_dyn_end - _start
267_dynsym_start_ofs:
268	.word __dynsym_start - _start
269
270	.globl	c_runtime_cpu_setup
271c_runtime_cpu_setup:
272
273	mov	pc, lr
274
275/*
276 *************************************************************************
277 *
278 * CPU_init_critical registers
279 *
280 * setup important registers
281 * setup memory timing
282 *
283 *************************************************************************
284 */
285
286
287#ifndef CONFIG_SKIP_LOWLEVEL_INIT
288cpu_init_crit:
289	/*
290	 * flush v4 I/D caches
291	 */
292	mov	r0, #0
293	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
294	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
295
296	/*
297	 * disable MMU stuff and caches
298	 */
299	mrc	p15, 0, r0, c1, c0, 0
300	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
301	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
302	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
303	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
304	mcr	p15, 0, r0, c1, c0, 0
305
306	/*
307	 * before relocating, we have to setup RAM timing
308	 * because memory timing is board-dependend, you will
309	 * find a lowlevel_init.S in your board directory.
310	 */
311	mov	ip, lr
312
313	bl	lowlevel_init
314
315	mov	lr, ip
316	mov	pc, lr
317#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
318
319/*
320 *************************************************************************
321 *
322 * Interrupt handling
323 *
324 *************************************************************************
325 */
326
327@
328@ IRQ stack frame.
329@
330#define S_FRAME_SIZE	72
331
332#define S_OLD_R0	68
333#define S_PSR		64
334#define S_PC		60
335#define S_LR		56
336#define S_SP		52
337
338#define S_IP		48
339#define S_FP		44
340#define S_R10		40
341#define S_R9		36
342#define S_R8		32
343#define S_R7		28
344#define S_R6		24
345#define S_R5		20
346#define S_R4		16
347#define S_R3		12
348#define S_R2		8
349#define S_R1		4
350#define S_R0		0
351
352#define MODE_SVC	0x13
353#define I_BIT		0x80
354
355/*
356 * use bad_save_user_regs for abort/prefetch/undef/swi ...
357 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
358 */
359
360	.macro	bad_save_user_regs
361	sub	sp, sp, #S_FRAME_SIZE
362	stmia	sp, {r0 - r12}			@ Calling r0-r12
363	ldr	r2, IRQ_STACK_START_IN
364	ldmia	r2, {r2 - r3}			@ get pc, cpsr
365	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
366
367	add	r5, sp, #S_SP
368	mov	r1, lr
369	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
370	mov	r0, sp
371	.endm
372
373	.macro	irq_save_user_regs
374	sub	sp, sp, #S_FRAME_SIZE
375	stmia	sp, {r0 - r12}			@ Calling r0-r12
376	add	r7, sp, #S_PC
377	stmdb	r7, {sp, lr}^			@ Calling SP, LR
378	str	lr, [r7, #0]			@ Save calling PC
379	mrs	r6, spsr
380	str	r6, [r7, #4]			@ Save CPSR
381	str	r0, [r7, #8]			@ Save OLD_R0
382	mov	r0, sp
383	.endm
384
385	.macro	irq_restore_user_regs
386	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
387	mov	r0, r0
388	ldr	lr, [sp, #S_PC]			@ Get PC
389	add	sp, sp, #S_FRAME_SIZE
390	/* return & move spsr_svc into cpsr */
391	subs	pc, lr, #4
392	.endm
393
394	.macro get_bad_stack
395	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
396
397	str	lr, [r13]			@ save caller lr / spsr
398	mrs	lr, spsr
399	str	lr, [r13, #4]
400
401	mov	r13, #MODE_SVC			@ prepare SVC-Mode
402	@ msr	spsr_c, r13
403	msr	spsr, r13
404	mov	lr, pc
405	movs	pc, lr
406	.endm
407
408	.macro get_irq_stack			@ setup IRQ stack
409	ldr	sp, IRQ_STACK_START
410	.endm
411
412	.macro get_fiq_stack			@ setup FIQ stack
413	ldr	sp, FIQ_STACK_START
414	.endm
415
416/*
417 * exception handlers
418 */
419	.align  5
420undefined_instruction:
421	get_bad_stack
422	bad_save_user_regs
423	bl	do_undefined_instruction
424
425	.align	5
426software_interrupt:
427	get_bad_stack
428	bad_save_user_regs
429	bl	do_software_interrupt
430
431	.align	5
432prefetch_abort:
433	get_bad_stack
434	bad_save_user_regs
435	bl	do_prefetch_abort
436
437	.align	5
438data_abort:
439	get_bad_stack
440	bad_save_user_regs
441	bl	do_data_abort
442
443	.align	5
444not_used:
445	get_bad_stack
446	bad_save_user_regs
447	bl	do_not_used
448
449#ifdef CONFIG_USE_IRQ
450
451	.align	5
452irq:
453	get_irq_stack
454	irq_save_user_regs
455	bl	do_irq
456	irq_restore_user_regs
457
458	.align	5
459fiq:
460	get_fiq_stack
461	/* someone ought to write a more effiction fiq_save_user_regs */
462	irq_save_user_regs
463	bl	do_fiq
464	irq_restore_user_regs
465
466#else
467
468	.align	5
469irq:
470	get_bad_stack
471	bad_save_user_regs
472	bl	do_irq
473
474	.align	5
475fiq:
476	get_bad_stack
477	bad_save_user_regs
478	bl	do_fiq
479
480#endif
481