xref: /openbmc/u-boot/arch/arm/cpu/arm920t/start.S (revision 301e8038) 
1/*
2 *  armboot - Startup Code for ARM920 CPU-core
3 *
4 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
5 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
6 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <asm-offsets.h>
28#include <common.h>
29#include <config.h>
30
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
41_start:	b	start_code
42	ldr	pc, _undefined_instruction
43	ldr	pc, _software_interrupt
44	ldr	pc, _prefetch_abort
45	ldr	pc, _data_abort
46	ldr	pc, _not_used
47	ldr	pc, _irq
48	ldr	pc, _fiq
49
50_undefined_instruction:	.word undefined_instruction
51_software_interrupt:	.word software_interrupt
52_prefetch_abort:	.word prefetch_abort
53_data_abort:		.word data_abort
54_not_used:		.word not_used
55_irq:			.word irq
56_fiq:			.word fiq
57
58	.balignl 16,0xdeadbeef
59
60
61/*
62 *************************************************************************
63 *
64 * Startup Code (called from the ARM reset exception vector)
65 *
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
68 * setup stack
69 * jump to second stage
70 *
71 *************************************************************************
72 */
73
74.globl _TEXT_BASE
75_TEXT_BASE:
76#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
77	.word	CONFIG_SPL_TEXT_BASE
78#else
79	.word	CONFIG_SYS_TEXT_BASE
80#endif
81
82/*
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
86 * them null.
87 */
88.globl _bss_start_ofs
89_bss_start_ofs:
90	.word __bss_start - _start
91
92.globl _bss_end_ofs
93_bss_end_ofs:
94	.word __bss_end - _start
95
96.globl _end_ofs
97_end_ofs:
98	.word _end - _start
99
100#ifdef CONFIG_USE_IRQ
101/* IRQ stack memory (calculated at run-time) */
102.globl IRQ_STACK_START
103IRQ_STACK_START:
104	.word	0x0badc0de
105
106/* IRQ stack memory (calculated at run-time) */
107.globl FIQ_STACK_START
108FIQ_STACK_START:
109	.word 0x0badc0de
110#endif
111
112/* IRQ stack memory (calculated at run-time) + 8 bytes */
113.globl IRQ_STACK_START_IN
114IRQ_STACK_START_IN:
115	.word	0x0badc0de
116
117/*
118 * the actual start code
119 */
120
121start_code:
122	/*
123	 * set the cpu to SVC32 mode
124	 */
125	mrs	r0, cpsr
126	bic	r0, r0, #0x1f
127	orr	r0, r0, #0xd3
128	msr	cpsr, r0
129
130#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
131	/*
132	 * relocate exception table
133	 */
134	ldr	r0, =_start
135	ldr	r1, =0x0
136	mov	r2, #16
137copyex:
138	subs	r2, r2, #1
139	ldr	r3, [r0], #4
140	str	r3, [r1], #4
141	bne	copyex
142#endif
143
144#ifdef CONFIG_S3C24X0
145	/* turn off the watchdog */
146
147# if defined(CONFIG_S3C2400)
148#  define pWTCON	0x15300000
149#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
150#  define CLKDIVN	0x14800014	/* clock divisor register */
151#else
152#  define pWTCON	0x53000000
153#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
154#  define INTSUBMSK	0x4A00001C
155#  define CLKDIVN	0x4C000014	/* clock divisor register */
156# endif
157
158	ldr	r0, =pWTCON
159	mov	r1, #0x0
160	str	r1, [r0]
161
162	/*
163	 * mask all IRQs by setting all bits in the INTMR - default
164	 */
165	mov	r1, #0xffffffff
166	ldr	r0, =INTMSK
167	str	r1, [r0]
168# if defined(CONFIG_S3C2410)
169	ldr	r1, =0x3ff
170	ldr	r0, =INTSUBMSK
171	str	r1, [r0]
172# endif
173
174	/* FCLK:HCLK:PCLK = 1:2:4 */
175	/* default FCLK is 120 MHz ! */
176	ldr	r0, =CLKDIVN
177	mov	r1, #3
178	str	r1, [r0]
179#endif	/* CONFIG_S3C24X0 */
180
181	/*
182	 * we do sys-critical inits only at reboot,
183	 * not when booting from ram!
184	 */
185#ifndef CONFIG_SKIP_LOWLEVEL_INIT
186	bl	cpu_init_crit
187#endif
188
189	bl	_main
190
191/*------------------------------------------------------------------------------*/
192
193	.globl	c_runtime_cpu_setup
194c_runtime_cpu_setup:
195
196	mov	pc, lr
197
198/*
199 *************************************************************************
200 *
201 * CPU_init_critical registers
202 *
203 * setup important registers
204 * setup memory timing
205 *
206 *************************************************************************
207 */
208
209
210#ifndef CONFIG_SKIP_LOWLEVEL_INIT
211cpu_init_crit:
212	/*
213	 * flush v4 I/D caches
214	 */
215	mov	r0, #0
216	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
217	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
218
219	/*
220	 * disable MMU stuff and caches
221	 */
222	mrc	p15, 0, r0, c1, c0, 0
223	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
224	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
225	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
226	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
227	mcr	p15, 0, r0, c1, c0, 0
228
229	/*
230	 * before relocating, we have to setup RAM timing
231	 * because memory timing is board-dependend, you will
232	 * find a lowlevel_init.S in your board directory.
233	 */
234	mov	ip, lr
235
236	bl	lowlevel_init
237
238	mov	lr, ip
239	mov	pc, lr
240#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
241
242/*
243 *************************************************************************
244 *
245 * Interrupt handling
246 *
247 *************************************************************************
248 */
249
250@
251@ IRQ stack frame.
252@
253#define S_FRAME_SIZE	72
254
255#define S_OLD_R0	68
256#define S_PSR		64
257#define S_PC		60
258#define S_LR		56
259#define S_SP		52
260
261#define S_IP		48
262#define S_FP		44
263#define S_R10		40
264#define S_R9		36
265#define S_R8		32
266#define S_R7		28
267#define S_R6		24
268#define S_R5		20
269#define S_R4		16
270#define S_R3		12
271#define S_R2		8
272#define S_R1		4
273#define S_R0		0
274
275#define MODE_SVC	0x13
276#define I_BIT		0x80
277
278/*
279 * use bad_save_user_regs for abort/prefetch/undef/swi ...
280 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
281 */
282
283	.macro	bad_save_user_regs
284	sub	sp, sp, #S_FRAME_SIZE
285	stmia	sp, {r0 - r12}			@ Calling r0-r12
286	ldr	r2, IRQ_STACK_START_IN
287	ldmia	r2, {r2 - r3}			@ get pc, cpsr
288	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
289
290	add	r5, sp, #S_SP
291	mov	r1, lr
292	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
293	mov	r0, sp
294	.endm
295
296	.macro	irq_save_user_regs
297	sub	sp, sp, #S_FRAME_SIZE
298	stmia	sp, {r0 - r12}			@ Calling r0-r12
299	add	r7, sp, #S_PC
300	stmdb	r7, {sp, lr}^			@ Calling SP, LR
301	str	lr, [r7, #0]			@ Save calling PC
302	mrs	r6, spsr
303	str	r6, [r7, #4]			@ Save CPSR
304	str	r0, [r7, #8]			@ Save OLD_R0
305	mov	r0, sp
306	.endm
307
308	.macro	irq_restore_user_regs
309	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
310	mov	r0, r0
311	ldr	lr, [sp, #S_PC]			@ Get PC
312	add	sp, sp, #S_FRAME_SIZE
313	/* return & move spsr_svc into cpsr */
314	subs	pc, lr, #4
315	.endm
316
317	.macro get_bad_stack
318	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
319
320	str	lr, [r13]			@ save caller lr / spsr
321	mrs	lr, spsr
322	str	lr, [r13, #4]
323
324	mov	r13, #MODE_SVC			@ prepare SVC-Mode
325	@ msr	spsr_c, r13
326	msr	spsr, r13
327	mov	lr, pc
328	movs	pc, lr
329	.endm
330
331	.macro get_irq_stack			@ setup IRQ stack
332	ldr	sp, IRQ_STACK_START
333	.endm
334
335	.macro get_fiq_stack			@ setup FIQ stack
336	ldr	sp, FIQ_STACK_START
337	.endm
338
339/*
340 * exception handlers
341 */
342	.align  5
343undefined_instruction:
344	get_bad_stack
345	bad_save_user_regs
346	bl	do_undefined_instruction
347
348	.align	5
349software_interrupt:
350	get_bad_stack
351	bad_save_user_regs
352	bl	do_software_interrupt
353
354	.align	5
355prefetch_abort:
356	get_bad_stack
357	bad_save_user_regs
358	bl	do_prefetch_abort
359
360	.align	5
361data_abort:
362	get_bad_stack
363	bad_save_user_regs
364	bl	do_data_abort
365
366	.align	5
367not_used:
368	get_bad_stack
369	bad_save_user_regs
370	bl	do_not_used
371
372#ifdef CONFIG_USE_IRQ
373
374	.align	5
375irq:
376	get_irq_stack
377	irq_save_user_regs
378	bl	do_irq
379	irq_restore_user_regs
380
381	.align	5
382fiq:
383	get_fiq_stack
384	/* someone ought to write a more effiction fiq_save_user_regs */
385	irq_save_user_regs
386	bl	do_fiq
387	irq_restore_user_regs
388
389#else
390
391	.align	5
392irq:
393	get_bad_stack
394	bad_save_user_regs
395	bl	do_irq
396
397	.align	5
398fiq:
399	get_bad_stack
400	bad_save_user_regs
401	bl	do_fiq
402
403#endif
404