1/* 2 * armboot - Startup Code for ARM920 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27#include <asm-offsets.h> 28#include <common.h> 29#include <config.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b start_code 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46 ldr pc, _not_used 47 ldr pc, _irq 48 ldr pc, _fiq 49 50_undefined_instruction: .word undefined_instruction 51_software_interrupt: .word software_interrupt 52_prefetch_abort: .word prefetch_abort 53_data_abort: .word data_abort 54_not_used: .word not_used 55_irq: .word irq 56_fiq: .word fiq 57 58 .balignl 16,0xdeadbeef 59 60 61/* 62 ************************************************************************* 63 * 64 * Startup Code (called from the ARM reset exception vector) 65 * 66 * do important init only if we don't start from memory! 67 * relocate armboot to ram 68 * setup stack 69 * jump to second stage 70 * 71 ************************************************************************* 72 */ 73 74.globl _TEXT_BASE 75_TEXT_BASE: 76 .word CONFIG_SYS_TEXT_BASE 77 78#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 79.globl _armboot_start 80_armboot_start: 81 .word _start 82#endif 83 84/* 85 * These are defined in the board-specific linker script. 86 */ 87.globl _bss_start 88_bss_start: 89 .word __bss_start 90 91.globl _bss_end 92_bss_end: 93 .word _end 94 95#ifdef CONFIG_USE_IRQ 96/* IRQ stack memory (calculated at run-time) */ 97.globl IRQ_STACK_START 98IRQ_STACK_START: 99 .word 0x0badc0de 100 101/* IRQ stack memory (calculated at run-time) */ 102.globl FIQ_STACK_START 103FIQ_STACK_START: 104 .word 0x0badc0de 105#endif 106 107#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 108/* IRQ stack memory (calculated at run-time) + 8 bytes */ 109.globl IRQ_STACK_START_IN 110IRQ_STACK_START_IN: 111 .word 0x0badc0de 112 113.globl _datarel_start 114_datarel_start: 115 .word __datarel_start 116 117.globl _datarelrolocal_start 118_datarelrolocal_start: 119 .word __datarelrolocal_start 120 121.globl _datarellocal_start 122_datarellocal_start: 123 .word __datarellocal_start 124 125.globl _datarelro_start 126_datarelro_start: 127 .word __datarelro_start 128 129.globl _got_start 130_got_start: 131 .word __got_start 132 133.globl _got_end 134_got_end: 135 .word __got_end 136 137/* 138 * the actual start code 139 */ 140 141start_code: 142 /* 143 * set the cpu to SVC32 mode 144 */ 145 mrs r0, cpsr 146 bic r0, r0, #0x1f 147 orr r0, r0, #0xd3 148 msr cpsr, r0 149 150 bl coloured_LED_init 151 bl red_LED_on 152 153#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) 154 /* 155 * relocate exception table 156 */ 157 ldr r0, =_start 158 ldr r1, =0x0 159 mov r2, #16 160copyex: 161 subs r2, r2, #1 162 ldr r3, [r0], #4 163 str r3, [r1], #4 164 bne copyex 165#endif 166 167#ifdef CONFIG_S3C24X0 168 /* turn off the watchdog */ 169 170# if defined(CONFIG_S3C2400) 171# define pWTCON 0x15300000 172# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ 173# define CLKDIVN 0x14800014 /* clock divisor register */ 174#else 175# define pWTCON 0x53000000 176# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ 177# define INTSUBMSK 0x4A00001C 178# define CLKDIVN 0x4C000014 /* clock divisor register */ 179# endif 180 181 ldr r0, =pWTCON 182 mov r1, #0x0 183 str r1, [r0] 184 185 /* 186 * mask all IRQs by setting all bits in the INTMR - default 187 */ 188 mov r1, #0xffffffff 189 ldr r0, =INTMSK 190 str r1, [r0] 191# if defined(CONFIG_S3C2410) 192 ldr r1, =0x3ff 193 ldr r0, =INTSUBMSK 194 str r1, [r0] 195# endif 196 197 /* FCLK:HCLK:PCLK = 1:2:4 */ 198 /* default FCLK is 120 MHz ! */ 199 ldr r0, =CLKDIVN 200 mov r1, #3 201 str r1, [r0] 202#endif /* CONFIG_S3C24X0 */ 203 204 /* 205 * we do sys-critical inits only at reboot, 206 * not when booting from ram! 207 */ 208#ifndef CONFIG_SKIP_LOWLEVEL_INIT 209 bl cpu_init_crit 210#endif 211 212/* Set stackpointer in internal RAM to call board_init_f */ 213call_board_init_f: 214 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 215 ldr r0,=0x00000000 216 bl board_init_f 217 218/*------------------------------------------------------------------------------*/ 219 220/* 221 * void relocate_code (addr_sp, gd, addr_moni) 222 * 223 * This "function" does not return, instead it continues in RAM 224 * after relocating the monitor code. 225 * 226 */ 227 .globl relocate_code 228relocate_code: 229 mov r4, r0 /* save addr_sp */ 230 mov r5, r1 /* save addr of gd */ 231 mov r6, r2 /* save addr of destination */ 232 mov r7, r2 /* save addr of destination */ 233 234 /* Set up the stack */ 235stack_setup: 236 mov sp, r4 237 238 adr r0, _start 239 ldr r2, _TEXT_BASE 240 ldr r3, _bss_start 241 sub r2, r3, r2 /* r2 <- size of armboot */ 242 add r2, r0, r2 /* r2 <- source end address */ 243 cmp r0, r6 244 beq clear_bss 245 246#ifndef CONFIG_SKIP_RELOCATE_UBOOT 247copy_loop: 248 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 249 stmia r6!, {r9-r10} /* copy to target address [r1] */ 250 cmp r0, r2 /* until source end address [r2] */ 251 blo copy_loop 252 253#ifndef CONFIG_PRELOADER 254 /* fix got entries */ 255 ldr r1, _TEXT_BASE /* Text base */ 256 mov r0, r7 /* reloc addr */ 257 ldr r2, _got_start /* addr in Flash */ 258 ldr r3, _got_end /* addr in Flash */ 259 sub r3, r3, r1 260 add r3, r3, r0 261 sub r2, r2, r1 262 add r2, r2, r0 263 264fixloop: 265 ldr r4, [r2] 266 sub r4, r4, r1 267 add r4, r4, r0 268 str r4, [r2] 269 add r2, r2, #4 270 cmp r2, r3 271 bne fixloop 272#endif 273#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ 274 275clear_bss: 276#ifndef CONFIG_PRELOADER 277 ldr r0, _bss_start 278 ldr r1, _bss_end 279 ldr r3, _TEXT_BASE /* Text base */ 280 mov r4, r7 /* reloc addr */ 281 sub r0, r0, r3 282 add r0, r0, r4 283 sub r1, r1, r3 284 add r1, r1, r4 285 mov r2, #0x00000000 /* clear */ 286 287clbss_l:str r2, [r0] /* clear loop... */ 288 add r0, r0, #4 289 cmp r0, r1 290 bne clbss_l 291 292 bl coloured_LED_init 293 bl red_LED_on 294#endif 295 296/* 297 * We are done. Do not return, instead branch to second part of board 298 * initialization, now running from RAM. 299 */ 300#ifdef CONFIG_NAND_SPL 301 ldr pc, _nand_boot 302 303_nand_boot: .word nand_boot 304#else 305 ldr r0, _TEXT_BASE 306 ldr r2, _board_init_r 307 sub r2, r2, r0 308 add r2, r2, r7 /* position from board_init_r in RAM */ 309 /* setup parameters for board_init_r */ 310 mov r0, r5 /* gd_t */ 311 mov r1, r7 /* dest_addr */ 312 /* jump to it ... */ 313 mov lr, r2 314 mov pc, lr 315 316_board_init_r: .word board_init_r 317#endif 318 319#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ 320/* 321 * the actual start code 322 */ 323 324start_code: 325 /* 326 * set the cpu to SVC32 mode 327 */ 328 mrs r0, cpsr 329 bic r0, r0, #0x1f 330 orr r0, r0, #0xd3 331 msr cpsr, r0 332 333 bl coloured_LED_init 334 bl red_LED_on 335 336#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) 337 /* 338 * relocate exception table 339 */ 340 ldr r0, =_start 341 ldr r1, =0x0 342 mov r2, #16 343copyex: 344 subs r2, r2, #1 345 ldr r3, [r0], #4 346 str r3, [r1], #4 347 bne copyex 348#endif 349 350#ifdef CONFIG_S3C24X0 351 /* turn off the watchdog */ 352 353# if defined(CONFIG_S3C2400) 354# define pWTCON 0x15300000 355# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ 356# define CLKDIVN 0x14800014 /* clock divisor register */ 357#else 358# define pWTCON 0x53000000 359# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ 360# define INTSUBMSK 0x4A00001C 361# define CLKDIVN 0x4C000014 /* clock divisor register */ 362# endif 363 364 ldr r0, =pWTCON 365 mov r1, #0x0 366 str r1, [r0] 367 368 /* 369 * mask all IRQs by setting all bits in the INTMR - default 370 */ 371 mov r1, #0xffffffff 372 ldr r0, =INTMSK 373 str r1, [r0] 374# if defined(CONFIG_S3C2410) 375 ldr r1, =0x3ff 376 ldr r0, =INTSUBMSK 377 str r1, [r0] 378# endif 379 380 /* FCLK:HCLK:PCLK = 1:2:4 */ 381 /* default FCLK is 120 MHz ! */ 382 ldr r0, =CLKDIVN 383 mov r1, #3 384 str r1, [r0] 385#endif /* CONFIG_S3C24X0 */ 386 387 /* 388 * we do sys-critical inits only at reboot, 389 * not when booting from ram! 390 */ 391#ifndef CONFIG_SKIP_LOWLEVEL_INIT 392 bl cpu_init_crit 393#endif 394 395#ifndef CONFIG_SKIP_RELOCATE_UBOOT 396relocate: /* relocate U-Boot to RAM */ 397 adr r0, _start /* r0 <- current position of code */ 398 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ 399 cmp r0, r1 /* don't reloc during debug */ 400 beq stack_setup 401 402 ldr r2, _armboot_start 403 ldr r3, _bss_start 404 sub r2, r3, r2 /* r2 <- size of armboot */ 405 add r2, r0, r2 /* r2 <- source end address */ 406 407copy_loop: 408 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 409 stmia r1!, {r3-r10} /* copy to target address [r1] */ 410 cmp r0, r2 /* until source end address [r2] */ 411 blo copy_loop 412#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ 413 414 /* Set up the stack */ 415stack_setup: 416 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ 417 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ 418 sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */ 419#ifdef CONFIG_USE_IRQ 420 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) 421#endif 422 sub sp, r0, #12 /* leave 3 words for abort-stack */ 423 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 424 425clear_bss: 426 ldr r0, _bss_start /* find start of bss segment */ 427 ldr r1, _bss_end /* stop here */ 428 mov r2, #0x00000000 /* clear */ 429 430clbss_l:str r2, [r0] /* clear loop... */ 431 add r0, r0, #4 432 cmp r0, r1 433 blo clbss_l 434 435 ldr pc, _start_armboot 436 437_start_armboot: .word start_armboot 438#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ 439 440/* 441 ************************************************************************* 442 * 443 * CPU_init_critical registers 444 * 445 * setup important registers 446 * setup memory timing 447 * 448 ************************************************************************* 449 */ 450 451 452#ifndef CONFIG_SKIP_LOWLEVEL_INIT 453cpu_init_crit: 454 /* 455 * flush v4 I/D caches 456 */ 457 mov r0, #0 458 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 459 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 460 461 /* 462 * disable MMU stuff and caches 463 */ 464 mrc p15, 0, r0, c1, c0, 0 465 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 466 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 467 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 468 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 469 mcr p15, 0, r0, c1, c0, 0 470 471 /* 472 * before relocating, we have to setup RAM timing 473 * because memory timing is board-dependend, you will 474 * find a lowlevel_init.S in your board directory. 475 */ 476 mov ip, lr 477 478 bl lowlevel_init 479 480 mov lr, ip 481 mov pc, lr 482#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 483 484/* 485 ************************************************************************* 486 * 487 * Interrupt handling 488 * 489 ************************************************************************* 490 */ 491 492@ 493@ IRQ stack frame. 494@ 495#define S_FRAME_SIZE 72 496 497#define S_OLD_R0 68 498#define S_PSR 64 499#define S_PC 60 500#define S_LR 56 501#define S_SP 52 502 503#define S_IP 48 504#define S_FP 44 505#define S_R10 40 506#define S_R9 36 507#define S_R8 32 508#define S_R7 28 509#define S_R6 24 510#define S_R5 20 511#define S_R4 16 512#define S_R3 12 513#define S_R2 8 514#define S_R1 4 515#define S_R0 0 516 517#define MODE_SVC 0x13 518#define I_BIT 0x80 519 520/* 521 * use bad_save_user_regs for abort/prefetch/undef/swi ... 522 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 523 */ 524 525 .macro bad_save_user_regs 526 sub sp, sp, #S_FRAME_SIZE 527 stmia sp, {r0 - r12} @ Calling r0-r12 528#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 529 ldr r2, _armboot_start 530 sub r2, r2, #(CONFIG_STACKSIZE) 531 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) 532 /* set base 2 words into abort stack */ 533 sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8) 534#else 535 ldr r2, IRQ_STACK_START_IN 536#endif 537 ldmia r2, {r2 - r3} @ get pc, cpsr 538 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 539 540 add r5, sp, #S_SP 541 mov r1, lr 542 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 543 mov r0, sp 544 .endm 545 546 .macro irq_save_user_regs 547 sub sp, sp, #S_FRAME_SIZE 548 stmia sp, {r0 - r12} @ Calling r0-r12 549 add r7, sp, #S_PC 550 stmdb r7, {sp, lr}^ @ Calling SP, LR 551 str lr, [r7, #0] @ Save calling PC 552 mrs r6, spsr 553 str r6, [r7, #4] @ Save CPSR 554 str r0, [r7, #8] @ Save OLD_R0 555 mov r0, sp 556 .endm 557 558 .macro irq_restore_user_regs 559 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 560 mov r0, r0 561 ldr lr, [sp, #S_PC] @ Get PC 562 add sp, sp, #S_FRAME_SIZE 563 /* return & move spsr_svc into cpsr */ 564 subs pc, lr, #4 565 .endm 566 567 .macro get_bad_stack 568#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 569 ldr r13, _armboot_start @ setup our mode stack 570 sub r13, r13, #(CONFIG_STACKSIZE) 571 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) 572 /* reserve a couple spots in abort stack */ 573 sub r13, r13, #(GENERATED_GBL_DATA_SIZE+8) 574#else 575 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 576#endif 577 578 str lr, [r13] @ save caller lr / spsr 579 mrs lr, spsr 580 str lr, [r13, #4] 581 582 mov r13, #MODE_SVC @ prepare SVC-Mode 583 @ msr spsr_c, r13 584 msr spsr, r13 585 mov lr, pc 586 movs pc, lr 587 .endm 588 589 .macro get_irq_stack @ setup IRQ stack 590 ldr sp, IRQ_STACK_START 591 .endm 592 593 .macro get_fiq_stack @ setup FIQ stack 594 ldr sp, FIQ_STACK_START 595 .endm 596 597/* 598 * exception handlers 599 */ 600 .align 5 601undefined_instruction: 602 get_bad_stack 603 bad_save_user_regs 604 bl do_undefined_instruction 605 606 .align 5 607software_interrupt: 608 get_bad_stack 609 bad_save_user_regs 610 bl do_software_interrupt 611 612 .align 5 613prefetch_abort: 614 get_bad_stack 615 bad_save_user_regs 616 bl do_prefetch_abort 617 618 .align 5 619data_abort: 620 get_bad_stack 621 bad_save_user_regs 622 bl do_data_abort 623 624 .align 5 625not_used: 626 get_bad_stack 627 bad_save_user_regs 628 bl do_not_used 629 630#ifdef CONFIG_USE_IRQ 631 632 .align 5 633irq: 634 get_irq_stack 635 irq_save_user_regs 636 bl do_irq 637 irq_restore_user_regs 638 639 .align 5 640fiq: 641 get_fiq_stack 642 /* someone ought to write a more effiction fiq_save_user_regs */ 643 irq_save_user_regs 644 bl do_fiq 645 irq_restore_user_regs 646 647#else 648 649 .align 5 650irq: 651 get_bad_stack 652 bad_save_user_regs 653 bl do_irq 654 655 .align 5 656fiq: 657 get_bad_stack 658 bad_save_user_regs 659 bl do_fiq 660 661#endif 662