xref: /openbmc/u-boot/arch/arm/cpu/arm920t/imx/timer.c (revision 63e22517)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2002
4  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5  * Marius Groeger <mgroeger@sysgo.de>
6  *
7  * (C) Copyright 2002
8  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9  * Alex Zuepke <azu@sysgo.de>
10  *
11  * (C) Copyright 2002
12  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
13  */
14 
15 #include <common.h>
16 #if defined (CONFIG_IMX)
17 
18 #include <asm/arch/imx-regs.h>
19 
20 int timer_init (void)
21 {
22 	int i;
23 	/* setup GP Timer 1 */
24 	TCTL1 = TCTL_SWR;
25 	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
26 	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
27 	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
28 
29 	/* Reset the timer */
30 	TCTL1 &= ~TCTL_TEN;
31 	TCTL1 |= TCTL_TEN; /* Enable timer */
32 
33 	return (0);
34 }
35 
36 /*
37  * timer without interrupts
38  */
39 ulong get_timer (ulong base)
40 {
41 	return get_timer_masked() - base;
42 }
43 
44 ulong get_timer_masked (void)
45 {
46 	return TCN1;
47 }
48 
49 void udelay_masked (unsigned long usec)
50 {
51 	ulong endtime = get_timer_masked() + usec;
52 	signed long diff;
53 
54 	do {
55 		ulong now = get_timer_masked ();
56 		diff = endtime - now;
57 	} while (diff >= 0);
58 }
59 
60 void __udelay (unsigned long usec)
61 {
62 	udelay_masked(usec);
63 }
64 
65 /*
66  * This function is derived from PowerPC code (read timebase as long long).
67  * On ARM it just returns the timer value.
68  */
69 unsigned long long get_ticks(void)
70 {
71 	return get_timer(0);
72 }
73 
74 /*
75  * This function is derived from PowerPC code (timebase clock frequency).
76  * On ARM it returns the number of timer ticks per second.
77  */
78 ulong get_tbclk (void)
79 {
80 	return CONFIG_SYS_HZ;
81 }
82 
83 /*
84  * Reset the cpu by setting up the watchdog timer and let him time out
85  */
86 void reset_cpu (ulong ignored)
87 {
88 	/* Disable watchdog and set Time-Out field to 0 */
89 	WCR = 0x00000000;
90 
91 	/* Write Service Sequence */
92 	WSR = 0x00005555;
93 	WSR = 0x0000AAAA;
94 
95 	/* Enable watchdog */
96 	WCR = 0x00000001;
97 
98 	while (1);
99 	/*NOTREACHED*/
100 }
101 
102 #endif /* defined (CONFIG_IMX) */
103