xref: /openbmc/u-boot/arch/arm/cpu/arm720t/start.S (revision eb0b43f2) 
1/*
2 *  armboot - Startup Code for ARM720 CPU-core
3 *
4 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
5 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <asm-offsets.h>
27#include <config.h>
28#include <version.h>
29#include <asm/hardware.h>
30
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
41_start: b	reset
42	ldr	pc, _undefined_instruction
43	ldr	pc, _software_interrupt
44	ldr	pc, _prefetch_abort
45	ldr	pc, _data_abort
46#ifdef CONFIG_LPC2292
47	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
48#else
49	ldr	pc, _not_used
50#endif
51	ldr	pc, _irq
52	ldr	pc, _fiq
53
54_undefined_instruction: .word undefined_instruction
55_software_interrupt:	.word software_interrupt
56_prefetch_abort:	.word prefetch_abort
57_data_abort:		.word data_abort
58_not_used:		.word not_used
59_irq:			.word irq
60_fiq:			.word fiq
61
62	.balignl 16,0xdeadbeef
63
64
65/*
66 *************************************************************************
67 *
68 * Startup Code (reset vector)
69 *
70 * do important init only if we don't start from RAM!
71 * relocate armboot to ram
72 * setup stack
73 * jump to second stage
74 *
75 *************************************************************************
76 */
77
78.globl _TEXT_BASE
79_TEXT_BASE:
80	.word	CONFIG_SYS_TEXT_BASE
81
82/*
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
86 * them null.
87 */
88.globl _bss_start_ofs
89_bss_start_ofs:
90	.word __bss_start - _start
91
92.globl _bss_end_ofs
93_bss_end_ofs:
94	.word __bss_end__ - _start
95
96.globl _end_ofs
97_end_ofs:
98	.word _end - _start
99
100#ifdef CONFIG_USE_IRQ
101/* IRQ stack memory (calculated at run-time) */
102.globl IRQ_STACK_START
103IRQ_STACK_START:
104	.word	0x0badc0de
105
106/* IRQ stack memory (calculated at run-time) */
107.globl FIQ_STACK_START
108FIQ_STACK_START:
109	.word 0x0badc0de
110#endif
111
112/* IRQ stack memory (calculated at run-time) + 8 bytes */
113.globl IRQ_STACK_START_IN
114IRQ_STACK_START_IN:
115	.word	0x0badc0de
116
117/*
118 * the actual reset code
119 */
120
121reset:
122	/*
123	 * set the cpu to SVC32 mode
124	 */
125	mrs	r0,cpsr
126	bic	r0,r0,#0x1f
127	orr	r0,r0,#0xd3
128	msr	cpsr,r0
129
130	/*
131	 * we do sys-critical inits only at reboot,
132	 * not when booting from ram!
133	 */
134#ifndef CONFIG_SKIP_LOWLEVEL_INIT
135	bl	cpu_init_crit
136#endif
137
138#ifdef CONFIG_LPC2292
139	bl	lowlevel_init
140#endif
141
142/* Set stackpointer in internal RAM to call board_init_f */
143call_board_init_f:
144	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
145	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
146	ldr	r0,=0x00000000
147	bl	board_init_f
148
149/*------------------------------------------------------------------------------*/
150
151/*
152 * void relocate_code (addr_sp, gd, addr_moni)
153 *
154 * This "function" does not return, instead it continues in RAM
155 * after relocating the monitor code.
156 *
157 */
158	.globl	relocate_code
159relocate_code:
160	mov	r4, r0	/* save addr_sp */
161	mov	r5, r1	/* save addr of gd */
162	mov	r6, r2	/* save addr of destination */
163
164	/* Set up the stack						    */
165stack_setup:
166	mov	sp, r4
167
168	adr	r0, _start
169	cmp	r0, r6
170	beq	clear_bss		/* skip relocation */
171	mov	r1, r6			/* r1 <- scratch for copy_loop */
172	ldr	r3, _bss_start_ofs
173	add	r2, r0, r3		/* r2 <- source end address	    */
174
175copy_loop:
176	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
177	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
178	cmp	r0, r2			/* until source end address [r2]    */
179	blo	copy_loop
180
181#ifndef CONFIG_SPL_BUILD
182	/*
183	 * fix .rel.dyn relocations
184	 */
185	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
186	sub	r9, r6, r0		/* r9 <- relocation offset */
187	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
188	add	r10, r10, r0		/* r10 <- sym table in FLASH */
189	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
190	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
191	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
192	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
193fixloop:
194	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
195	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
196	ldr	r1, [r2, #4]
197	and	r7, r1, #0xff
198	cmp	r7, #23			/* relative fixup? */
199	beq	fixrel
200	cmp	r7, #2			/* absolute fixup? */
201	beq	fixabs
202	/* ignore unknown type of fixup */
203	b	fixnext
204fixabs:
205	/* absolute fix: set location to (offset) symbol value */
206	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
207	add	r1, r10, r1		/* r1 <- address of symbol in table */
208	ldr	r1, [r1, #4]		/* r1 <- symbol value */
209	add	r1, r1, r9		/* r1 <- relocated sym addr */
210	b	fixnext
211fixrel:
212	/* relative fix: increase location by offset */
213	ldr	r1, [r0]
214	add	r1, r1, r9
215fixnext:
216	str	r1, [r0]
217	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
218	cmp	r2, r3
219	blo	fixloop
220#endif
221
222clear_bss:
223#ifndef CONFIG_SPL_BUILD
224	ldr	r0, _bss_start_ofs
225	ldr	r1, _bss_end_ofs
226	mov	r4, r6			/* reloc addr */
227	add	r0, r0, r4
228	add	r1, r1, r4
229	mov	r2, #0x00000000		/* clear			    */
230
231clbss_l:cmp	r0, r1			/* clear loop... */
232	bhs	clbss_e			/* if reached end of bss, exit */
233	str	r2, [r0]
234	add	r0, r0, #4
235	b	clbss_l
236clbss_e:
237
238	bl coloured_LED_init
239	bl red_led_on
240#endif
241
242/*
243 * We are done. Do not return, instead branch to second part of board
244 * initialization, now running from RAM.
245 */
246	ldr	r0, _board_init_r_ofs
247	adr	r1, _start
248	add	lr, r0, r1
249	add	lr, lr, r9
250	/* setup parameters for board_init_r */
251	mov	r0, r5		/* gd_t */
252	mov	r1, r6		/* dest_addr */
253	/* jump to it ... */
254	mov	pc, lr
255
256_board_init_r_ofs:
257	.word board_init_r - _start
258
259_rel_dyn_start_ofs:
260	.word __rel_dyn_start - _start
261_rel_dyn_end_ofs:
262	.word __rel_dyn_end - _start
263_dynsym_start_ofs:
264	.word __dynsym_start - _start
265
266/*
267 *************************************************************************
268 *
269 * CPU_init_critical registers
270 *
271 * setup important registers
272 * setup memory timing
273 *
274 *************************************************************************
275 */
276
277#if defined(CONFIG_LPC2292)
278PLLCFG_ADR:	.word	PLLCFG
279PLLFEED_ADR:	.word	PLLFEED
280PLLCON_ADR:	.word	PLLCON
281PLLSTAT_ADR:	.word	PLLSTAT
282VPBDIV_ADR:	.word	VPBDIV
283MEMMAP_ADR:	.word	MEMMAP
284
285#endif
286
287cpu_init_crit:
288#if defined(CONFIG_NETARM)
289	/*
290	 * prior to software reset : need to set pin PORTC4 to be *HRESET
291	 */
292	ldr	r0, =NETARM_GEN_MODULE_BASE
293	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
294			NETARM_GEN_PORT_DIR(0x10))
295	str	r1, [r0, #+NETARM_GEN_PORTC]
296	/*
297	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
298	 *		    for an explanation of this process
299	 */
300	ldr	r0, =NETARM_GEN_MODULE_BASE
301	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
302	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
303	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
304	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
305	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
306	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
307	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
308	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
309	/*
310	 * setup PLL and System Config
311	 */
312	ldr	r0, =NETARM_GEN_MODULE_BASE
313
314	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
315			NETARM_GEN_SYS_CFG_BUSFULL | \
316			NETARM_GEN_SYS_CFG_USER_EN | \
317			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
318			NETARM_GEN_SYS_CFG_BUSARB_INT | \
319			NETARM_GEN_SYS_CFG_BUSMON_EN )
320
321	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
322
323#ifndef CONFIG_NETARM_PLL_BYPASS
324	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
325			NETARM_GEN_PLL_CTL_POLTST_DEF | \
326			NETARM_GEN_PLL_CTL_INDIV(1) | \
327			NETARM_GEN_PLL_CTL_ICP_DEF | \
328			NETARM_GEN_PLL_CTL_OUTDIV(2) )
329	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
330#endif
331
332	/*
333	 * mask all IRQs by clearing all bits in the INTMRs
334	 */
335	mov	r1, #0
336	ldr	r0, =NETARM_GEN_MODULE_BASE
337	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
338
339#elif defined(CONFIG_S3C4510B)
340
341	/*
342	 * Mask off all IRQ sources
343	 */
344	ldr	r1, =REG_INTMASK
345	ldr	r0, =0x3FFFFF
346	str	r0, [r1]
347
348	/*
349	 * Disable Cache
350	 */
351	ldr r0, =REG_SYSCFG
352	ldr r1, =0x83ffffa0	/* cache-disabled  */
353	str r1, [r0]
354
355#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
356	/* No specific initialisation for IntegratorAP/CM720T as yet */
357#elif defined(CONFIG_LPC2292)
358	/* Set-up PLL */
359	mov	r3, #0xAA
360	mov	r4, #0x55
361	/* First disconnect and disable the PLL */
362	ldr	r0, PLLCON_ADR
363	mov	r1, #0x00
364	str	r1, [r0]
365	ldr	r0, PLLFEED_ADR /* start feed sequence */
366	str	r3, [r0]
367	str	r4, [r0]	/* feed sequence done */
368	/* Set new M and P values */
369	ldr	r0, PLLCFG_ADR
370	mov	r1, #0x23	/* M=4 and P=2 */
371	str	r1, [r0]
372	ldr	r0, PLLFEED_ADR /* start feed sequence */
373	str	r3, [r0]
374	str	r4, [r0]	/* feed sequence done */
375	/* Then enable the PLL */
376	ldr	r0, PLLCON_ADR
377	mov	r1, #0x01	/* PLL enable bit */
378	str	r1, [r0]
379	ldr	r0, PLLFEED_ADR /* start feed sequence */
380	str	r3, [r0]
381	str	r4, [r0]	/* feed sequence done */
382	/* Wait for the lock */
383	ldr	r0, PLLSTAT_ADR
384	mov	r1, #0x400	/* lock bit */
385lock_loop:
386	ldr	r2, [r0]
387	and	r2, r1, r2
388	cmp	r2, #0
389	beq	lock_loop
390	/* And finally connect the PLL */
391	ldr	r0, PLLCON_ADR
392	mov	r1, #0x03	/* PLL enable bit and connect bit */
393	str	r1, [r0]
394	ldr	r0, PLLFEED_ADR /* start feed sequence */
395	str	r3, [r0]
396	str	r4, [r0]	/* feed sequence done */
397	/* Set-up VPBDIV register */
398	ldr	r0, VPBDIV_ADR
399	mov	r1, #0x01	/* VPB clock is same as process clock */
400	str	r1, [r0]
401#else
402#error No cpu_init_crit() defined for current CPU type
403#endif
404
405#ifdef CONFIG_ARM7_REVD
406	/* set clock speed */
407	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
408	/* !!! not doing DRAM refresh properly! */
409	ldr	r0, SYSCON3
410	ldr	r1, [r0]
411	bic	r1, r1, #CLKCTL
412	orr	r1, r1, #CLKCTL_36
413	str	r1, [r0]
414#endif
415
416#ifndef CONFIG_LPC2292
417	mov	ip, lr
418	/*
419	 * before relocating, we have to setup RAM timing
420	 * because memory timing is board-dependent, you will
421	 * find a lowlevel_init.S in your board directory.
422	 */
423	bl	lowlevel_init
424	mov	lr, ip
425#endif
426
427	mov	pc, lr
428
429
430/*
431 *************************************************************************
432 *
433 * Interrupt handling
434 *
435 *************************************************************************
436 */
437
438@
439@ IRQ stack frame.
440@
441#define S_FRAME_SIZE	72
442
443#define S_OLD_R0	68
444#define S_PSR		64
445#define S_PC		60
446#define S_LR		56
447#define S_SP		52
448
449#define S_IP		48
450#define S_FP		44
451#define S_R10		40
452#define S_R9		36
453#define S_R8		32
454#define S_R7		28
455#define S_R6		24
456#define S_R5		20
457#define S_R4		16
458#define S_R3		12
459#define S_R2		8
460#define S_R1		4
461#define S_R0		0
462
463#define MODE_SVC 0x13
464#define I_BIT	 0x80
465
466/*
467 * use bad_save_user_regs for abort/prefetch/undef/swi ...
468 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
469 */
470
471	.macro	bad_save_user_regs
472	sub	sp, sp, #S_FRAME_SIZE
473	stmia	sp, {r0 - r12}			@ Calling r0-r12
474	add	r8, sp, #S_PC
475
476	ldr	r2, IRQ_STACK_START_IN
477	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
478	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
479
480	add	r5, sp, #S_SP
481	mov	r1, lr
482	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
483	mov	r0, sp
484	.endm
485
486	.macro	irq_save_user_regs
487	sub	sp, sp, #S_FRAME_SIZE
488	stmia	sp, {r0 - r12}			@ Calling r0-r12
489	add	r8, sp, #S_PC
490	stmdb	r8, {sp, lr}^			@ Calling SP, LR
491	str	lr, [r8, #0]			@ Save calling PC
492	mrs	r6, spsr
493	str	r6, [r8, #4]			@ Save CPSR
494	str	r0, [r8, #8]			@ Save OLD_R0
495	mov	r0, sp
496	.endm
497
498	.macro	irq_restore_user_regs
499	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
500	mov	r0, r0
501	ldr	lr, [sp, #S_PC]			@ Get PC
502	add	sp, sp, #S_FRAME_SIZE
503	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
504	.endm
505
506	.macro get_bad_stack
507	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
508
509	str	lr, [r13]			@ save caller lr / spsr
510	mrs	lr, spsr
511	str	lr, [r13, #4]
512
513	mov	r13, #MODE_SVC			@ prepare SVC-Mode
514	msr	spsr_c, r13
515	mov	lr, pc
516	movs	pc, lr
517	.endm
518
519	.macro get_irq_stack			@ setup IRQ stack
520	ldr	sp, IRQ_STACK_START
521	.endm
522
523	.macro get_fiq_stack			@ setup FIQ stack
524	ldr	sp, FIQ_STACK_START
525	.endm
526
527/*
528 * exception handlers
529 */
530	.align	5
531undefined_instruction:
532	get_bad_stack
533	bad_save_user_regs
534	bl	do_undefined_instruction
535
536	.align	5
537software_interrupt:
538	get_bad_stack
539	bad_save_user_regs
540	bl	do_software_interrupt
541
542	.align	5
543prefetch_abort:
544	get_bad_stack
545	bad_save_user_regs
546	bl	do_prefetch_abort
547
548	.align	5
549data_abort:
550	get_bad_stack
551	bad_save_user_regs
552	bl	do_data_abort
553
554	.align	5
555not_used:
556	get_bad_stack
557	bad_save_user_regs
558	bl	do_not_used
559
560#ifdef CONFIG_USE_IRQ
561
562	.align	5
563irq:
564	get_irq_stack
565	irq_save_user_regs
566	bl	do_irq
567	irq_restore_user_regs
568
569	.align	5
570fiq:
571	get_fiq_stack
572	/* someone ought to write a more effiction fiq_save_user_regs */
573	irq_save_user_regs
574	bl	do_fiq
575	irq_restore_user_regs
576
577#else
578
579	.align	5
580irq:
581	get_bad_stack
582	bad_save_user_regs
583	bl	do_irq
584
585	.align	5
586fiq:
587	get_bad_stack
588	bad_save_user_regs
589	bl	do_fiq
590
591#endif
592
593#if defined(CONFIG_NETARM)
594	.align	5
595.globl reset_cpu
596reset_cpu:
597	ldr	r1, =NETARM_MEM_MODULE_BASE
598	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
599	ldr	r1, =0xFFFFF000
600	and	r0, r1, r0
601	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
602	add	r0, r1, r0
603	ldr	r4, =NETARM_GEN_MODULE_BASE
604	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
605	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
606	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
607	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
608	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
609	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
610	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
611	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
612	mov	pc, r0
613#elif defined(CONFIG_S3C4510B)
614/* Nothing done here as reseting the CPU is board specific, depending
615 * on external peripherals such as watchdog timers, etc. */
616#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
617	/* No specific reset actions for IntegratorAP/CM720T as yet */
618#elif defined(CONFIG_LPC2292)
619	.align	5
620.globl reset_cpu
621reset_cpu:
622	mov	pc, r0
623#else
624#error No reset_cpu() defined for current CPU type
625#endif
626