1/* 2 * armboot - Startup Code for ARM720 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 27#include <config.h> 28#include <version.h> 29#include <asm/hardware.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b reset 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46#ifdef CONFIG_LPC2292 47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */ 48#else 49 ldr pc, _not_used 50#endif 51 ldr pc, _irq 52 ldr pc, _fiq 53 54_undefined_instruction: .word undefined_instruction 55_software_interrupt: .word software_interrupt 56_prefetch_abort: .word prefetch_abort 57_data_abort: .word data_abort 58_not_used: .word not_used 59_irq: .word irq 60_fiq: .word fiq 61 62 .balignl 16,0xdeadbeef 63 64 65/* 66 ************************************************************************* 67 * 68 * Startup Code (reset vector) 69 * 70 * do important init only if we don't start from RAM! 71 * relocate armboot to ram 72 * setup stack 73 * jump to second stage 74 * 75 ************************************************************************* 76 */ 77 78_TEXT_BASE: 79 .word TEXT_BASE 80 81.globl _armboot_start 82_armboot_start: 83 .word _start 84 85/* 86 * These are defined in the board-specific linker script. 87 */ 88.globl _bss_start 89_bss_start: 90 .word __bss_start 91 92.globl _bss_end 93_bss_end: 94 .word _end 95 96#ifdef CONFIG_USE_IRQ 97/* IRQ stack memory (calculated at run-time) */ 98.globl IRQ_STACK_START 99IRQ_STACK_START: 100 .word 0x0badc0de 101 102/* IRQ stack memory (calculated at run-time) */ 103.globl FIQ_STACK_START 104FIQ_STACK_START: 105 .word 0x0badc0de 106#endif 107 108 109/* 110 * the actual reset code 111 */ 112 113reset: 114 /* 115 * set the cpu to SVC32 mode 116 */ 117 mrs r0,cpsr 118 bic r0,r0,#0x1f 119 orr r0,r0,#0x13 120 msr cpsr,r0 121 122 /* 123 * we do sys-critical inits only at reboot, 124 * not when booting from ram! 125 */ 126#ifndef CONFIG_SKIP_LOWLEVEL_INIT 127 bl cpu_init_crit 128#endif 129 130#ifdef CONFIG_LPC2292 131 bl lowlevel_init 132#endif 133 134#ifndef CONFIG_SKIP_RELOCATE_UBOOT 135relocate: /* relocate U-Boot to RAM */ 136 adr r0, _start /* r0 <- current position of code */ 137 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ 138 cmp r0, r1 /* don't reloc during debug */ 139 beq stack_setup 140 141#if TEXT_BASE 142#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */ 143 ldr r2, =0x0 /* Relocate the exception vectors */ 144 cmp r1, r2 /* and associated data to address */ 145 ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */ 146 stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */ 147 ldmneia r0, {r3-r9} 148 stmneia r2, {r3-r9} 149 adrne r0, _start /* restore r0 */ 150#endif /* !CONFIG_LPC2292 */ 151#endif 152 153 ldr r2, _armboot_start 154 ldr r3, _bss_start 155 sub r2, r3, r2 /* r2 <- size of armboot */ 156 add r2, r0, r2 /* r2 <- source end address */ 157 158copy_loop: 159 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 160 stmia r1!, {r3-r10} /* copy to target address [r1] */ 161 cmp r0, r2 /* until source end addreee [r2] */ 162 ble copy_loop 163 164#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ 165 166 /* Set up the stack */ 167stack_setup: 168 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ 169 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ 170 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ 171#ifdef CONFIG_USE_IRQ 172 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) 173#endif 174 sub sp, r0, #12 /* leave 3 words for abort-stack */ 175 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 176 177clear_bss: 178 ldr r0, _bss_start /* find start of bss segment */ 179 ldr r1, _bss_end /* stop here */ 180 mov r2, #0x00000000 /* clear */ 181 182clbss_l:str r2, [r0] /* clear loop... */ 183 add r0, r0, #4 184 cmp r0, r1 185 ble clbss_l 186 187 ldr pc, _start_armboot 188 189_start_armboot: .word start_armboot 190 191/* 192 ************************************************************************* 193 * 194 * CPU_init_critical registers 195 * 196 * setup important registers 197 * setup memory timing 198 * 199 ************************************************************************* 200 */ 201 202#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) 203 204/* Interupt-Controller base addresses */ 205INTMR1: .word 0x80000280 @ 32 bit size 206INTMR2: .word 0x80001280 @ 16 bit size 207INTMR3: .word 0x80002280 @ 8 bit size 208 209/* SYSCONs */ 210SYSCON1: .word 0x80000100 211SYSCON2: .word 0x80001100 212SYSCON3: .word 0x80002200 213 214#define CLKCTL 0x6 /* mask */ 215#define CLKCTL_18 0x0 /* 18.432 MHz */ 216#define CLKCTL_36 0x2 /* 36.864 MHz */ 217#define CLKCTL_49 0x4 /* 49.152 MHz */ 218#define CLKCTL_73 0x6 /* 73.728 MHz */ 219 220#elif defined(CONFIG_LPC2292) 221PLLCFG_ADR: .word PLLCFG 222PLLFEED_ADR: .word PLLFEED 223PLLCON_ADR: .word PLLCON 224PLLSTAT_ADR: .word PLLSTAT 225VPBDIV_ADR: .word VPBDIV 226MEMMAP_ADR: .word MEMMAP 227 228#endif 229 230cpu_init_crit: 231#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) 232 233 /* 234 * mask all IRQs by clearing all bits in the INTMRs 235 */ 236 mov r1, #0x00 237 ldr r0, INTMR1 238 str r1, [r0] 239 ldr r0, INTMR2 240 str r1, [r0] 241 ldr r0, INTMR3 242 str r1, [r0] 243 244 /* 245 * flush v4 I/D caches 246 */ 247 mov r0, #0 248 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 249 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 250 251 /* 252 * disable MMU stuff and caches 253 */ 254 mrc p15,0,r0,c1,c0 255 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 256 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) 257 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 258 mcr p15,0,r0,c1,c0 259#elif defined(CONFIG_NETARM) 260 /* 261 * prior to software reset : need to set pin PORTC4 to be *HRESET 262 */ 263 ldr r0, =NETARM_GEN_MODULE_BASE 264 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ 265 NETARM_GEN_PORT_DIR(0x10)) 266 str r1, [r0, #+NETARM_GEN_PORTC] 267 /* 268 * software reset : see HW Ref. Guide 8.2.4 : Software Service register 269 * for an explanation of this process 270 */ 271 ldr r0, =NETARM_GEN_MODULE_BASE 272 ldr r1, =NETARM_GEN_SW_SVC_RESETA 273 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 274 ldr r1, =NETARM_GEN_SW_SVC_RESETB 275 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 276 ldr r1, =NETARM_GEN_SW_SVC_RESETA 277 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 278 ldr r1, =NETARM_GEN_SW_SVC_RESETB 279 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] 280 /* 281 * setup PLL and System Config 282 */ 283 ldr r0, =NETARM_GEN_MODULE_BASE 284 285 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ 286 NETARM_GEN_SYS_CFG_BUSFULL | \ 287 NETARM_GEN_SYS_CFG_USER_EN | \ 288 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ 289 NETARM_GEN_SYS_CFG_BUSARB_INT | \ 290 NETARM_GEN_SYS_CFG_BUSMON_EN ) 291 292 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] 293 294#ifndef CONFIG_NETARM_PLL_BYPASS 295 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ 296 NETARM_GEN_PLL_CTL_POLTST_DEF | \ 297 NETARM_GEN_PLL_CTL_INDIV(1) | \ 298 NETARM_GEN_PLL_CTL_ICP_DEF | \ 299 NETARM_GEN_PLL_CTL_OUTDIV(2) ) 300 str r1, [r0, #+NETARM_GEN_PLL_CONTROL] 301#endif 302 303 /* 304 * mask all IRQs by clearing all bits in the INTMRs 305 */ 306 mov r1, #0 307 ldr r0, =NETARM_GEN_MODULE_BASE 308 str r1, [r0, #+NETARM_GEN_INTR_ENABLE] 309 310#elif defined(CONFIG_S3C4510B) 311 312 /* 313 * Mask off all IRQ sources 314 */ 315 ldr r1, =REG_INTMASK 316 ldr r0, =0x3FFFFF 317 str r0, [r1] 318 319 /* 320 * Disable Cache 321 */ 322 ldr r0, =REG_SYSCFG 323 ldr r1, =0x83ffffa0 /* cache-disabled */ 324 str r1, [r0] 325 326#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) 327 /* No specific initialisation for IntegratorAP/CM720T as yet */ 328#elif defined(CONFIG_LPC2292) 329 /* Set-up PLL */ 330 mov r3, #0xAA 331 mov r4, #0x55 332 /* First disconnect and disable the PLL */ 333 ldr r0, PLLCON_ADR 334 mov r1, #0x00 335 str r1, [r0] 336 ldr r0, PLLFEED_ADR /* start feed sequence */ 337 str r3, [r0] 338 str r4, [r0] /* feed sequence done */ 339 /* Set new M and P values */ 340 ldr r0, PLLCFG_ADR 341 mov r1, #0x23 /* M=4 and P=2 */ 342 str r1, [r0] 343 ldr r0, PLLFEED_ADR /* start feed sequence */ 344 str r3, [r0] 345 str r4, [r0] /* feed sequence done */ 346 /* Then enable the PLL */ 347 ldr r0, PLLCON_ADR 348 mov r1, #0x01 /* PLL enable bit */ 349 str r1, [r0] 350 ldr r0, PLLFEED_ADR /* start feed sequence */ 351 str r3, [r0] 352 str r4, [r0] /* feed sequence done */ 353 /* Wait for the lock */ 354 ldr r0, PLLSTAT_ADR 355 mov r1, #0x400 /* lock bit */ 356lock_loop: 357 ldr r2, [r0] 358 and r2, r1, r2 359 cmp r2, #0 360 beq lock_loop 361 /* And finally connect the PLL */ 362 ldr r0, PLLCON_ADR 363 mov r1, #0x03 /* PLL enable bit and connect bit */ 364 str r1, [r0] 365 ldr r0, PLLFEED_ADR /* start feed sequence */ 366 str r3, [r0] 367 str r4, [r0] /* feed sequence done */ 368 /* Set-up VPBDIV register */ 369 ldr r0, VPBDIV_ADR 370 mov r1, #0x01 /* VPB clock is same as process clock */ 371 str r1, [r0] 372#else 373#error No cpu_init_crit() defined for current CPU type 374#endif 375 376#ifdef CONFIG_ARM7_REVD 377 /* set clock speed */ 378 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */ 379 /* !!! not doing DRAM refresh properly! */ 380 ldr r0, SYSCON3 381 ldr r1, [r0] 382 bic r1, r1, #CLKCTL 383 orr r1, r1, #CLKCTL_36 384 str r1, [r0] 385#endif 386 387#ifndef CONFIG_LPC2292 388 mov ip, lr 389 /* 390 * before relocating, we have to setup RAM timing 391 * because memory timing is board-dependent, you will 392 * find a lowlevel_init.S in your board directory. 393 */ 394 bl lowlevel_init 395 mov lr, ip 396#endif 397 398 mov pc, lr 399 400 401/* 402 ************************************************************************* 403 * 404 * Interrupt handling 405 * 406 ************************************************************************* 407 */ 408 409@ 410@ IRQ stack frame. 411@ 412#define S_FRAME_SIZE 72 413 414#define S_OLD_R0 68 415#define S_PSR 64 416#define S_PC 60 417#define S_LR 56 418#define S_SP 52 419 420#define S_IP 48 421#define S_FP 44 422#define S_R10 40 423#define S_R9 36 424#define S_R8 32 425#define S_R7 28 426#define S_R6 24 427#define S_R5 20 428#define S_R4 16 429#define S_R3 12 430#define S_R2 8 431#define S_R1 4 432#define S_R0 0 433 434#define MODE_SVC 0x13 435#define I_BIT 0x80 436 437/* 438 * use bad_save_user_regs for abort/prefetch/undef/swi ... 439 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 440 */ 441 442 .macro bad_save_user_regs 443 sub sp, sp, #S_FRAME_SIZE 444 stmia sp, {r0 - r12} @ Calling r0-r12 445 add r8, sp, #S_PC 446 447 ldr r2, _armboot_start 448 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) 449 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack 450 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 451 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 452 453 add r5, sp, #S_SP 454 mov r1, lr 455 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 456 mov r0, sp 457 .endm 458 459 .macro irq_save_user_regs 460 sub sp, sp, #S_FRAME_SIZE 461 stmia sp, {r0 - r12} @ Calling r0-r12 462 add r8, sp, #S_PC 463 stmdb r8, {sp, lr}^ @ Calling SP, LR 464 str lr, [r8, #0] @ Save calling PC 465 mrs r6, spsr 466 str r6, [r8, #4] @ Save CPSR 467 str r0, [r8, #8] @ Save OLD_R0 468 mov r0, sp 469 .endm 470 471 .macro irq_restore_user_regs 472 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 473 mov r0, r0 474 ldr lr, [sp, #S_PC] @ Get PC 475 add sp, sp, #S_FRAME_SIZE 476 subs pc, lr, #4 @ return & move spsr_svc into cpsr 477 .endm 478 479 .macro get_bad_stack 480 ldr r13, _armboot_start @ setup our mode stack 481 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) 482 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack 483 484 str lr, [r13] @ save caller lr / spsr 485 mrs lr, spsr 486 str lr, [r13, #4] 487 488 mov r13, #MODE_SVC @ prepare SVC-Mode 489 msr spsr_c, r13 490 mov lr, pc 491 movs pc, lr 492 .endm 493 494 .macro get_irq_stack @ setup IRQ stack 495 ldr sp, IRQ_STACK_START 496 .endm 497 498 .macro get_fiq_stack @ setup FIQ stack 499 ldr sp, FIQ_STACK_START 500 .endm 501 502/* 503 * exception handlers 504 */ 505 .align 5 506undefined_instruction: 507 get_bad_stack 508 bad_save_user_regs 509 bl do_undefined_instruction 510 511 .align 5 512software_interrupt: 513 get_bad_stack 514 bad_save_user_regs 515 bl do_software_interrupt 516 517 .align 5 518prefetch_abort: 519 get_bad_stack 520 bad_save_user_regs 521 bl do_prefetch_abort 522 523 .align 5 524data_abort: 525 get_bad_stack 526 bad_save_user_regs 527 bl do_data_abort 528 529 .align 5 530not_used: 531 get_bad_stack 532 bad_save_user_regs 533 bl do_not_used 534 535#ifdef CONFIG_USE_IRQ 536 537 .align 5 538irq: 539 get_irq_stack 540 irq_save_user_regs 541 bl do_irq 542 irq_restore_user_regs 543 544 .align 5 545fiq: 546 get_fiq_stack 547 /* someone ought to write a more effiction fiq_save_user_regs */ 548 irq_save_user_regs 549 bl do_fiq 550 irq_restore_user_regs 551 552#else 553 554 .align 5 555irq: 556 get_bad_stack 557 bad_save_user_regs 558 bl do_irq 559 560 .align 5 561fiq: 562 get_bad_stack 563 bad_save_user_regs 564 bl do_fiq 565 566#endif 567 568#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) 569 .align 5 570.globl reset_cpu 571reset_cpu: 572 mov ip, #0 573 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 574 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 575 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 576 bic ip, ip, #0x000f @ ............wcam 577 bic ip, ip, #0x2100 @ ..v....s........ 578 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 579 mov pc, r0 580#elif defined(CONFIG_NETARM) 581 .align 5 582.globl reset_cpu 583reset_cpu: 584 ldr r1, =NETARM_MEM_MODULE_BASE 585 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] 586 ldr r1, =0xFFFFF000 587 and r0, r1, r0 588 ldr r1, =(relocate-TEXT_BASE) 589 add r0, r1, r0 590 ldr r4, =NETARM_GEN_MODULE_BASE 591 ldr r1, =NETARM_GEN_SW_SVC_RESETA 592 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 593 ldr r1, =NETARM_GEN_SW_SVC_RESETB 594 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 595 ldr r1, =NETARM_GEN_SW_SVC_RESETA 596 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 597 ldr r1, =NETARM_GEN_SW_SVC_RESETB 598 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] 599 mov pc, r0 600#elif defined(CONFIG_S3C4510B) 601/* Nothing done here as reseting the CPU is board specific, depending 602 * on external peripherals such as watchdog timers, etc. */ 603#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) 604 /* No specific reset actions for IntegratorAP/CM720T as yet */ 605#elif defined(CONFIG_LPC2292) 606 .align 5 607.globl reset_cpu 608reset_cpu: 609 mov pc, r0 610#else 611#error No reset_cpu() defined for current CPU type 612#endif 613