1/* 2 * armboot - Startup Code for ARM720 CPU-core 3 * 4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#include <asm-offsets.h> 27#include <config.h> 28#include <version.h> 29#include <asm/hardware.h> 30 31/* 32 ************************************************************************* 33 * 34 * Jump vector table as in table 3.1 in [1] 35 * 36 ************************************************************************* 37 */ 38 39 40.globl _start 41_start: b reset 42 ldr pc, _undefined_instruction 43 ldr pc, _software_interrupt 44 ldr pc, _prefetch_abort 45 ldr pc, _data_abort 46 ldr pc, _not_used 47 ldr pc, _irq 48 ldr pc, _fiq 49 50#ifdef CONFIG_SPL_BUILD 51_undefined_instruction: .word _undefined_instruction 52_software_interrupt: .word _software_interrupt 53_prefetch_abort: .word _prefetch_abort 54_data_abort: .word _data_abort 55_not_used: .word _not_used 56_irq: .word _irq 57_fiq: .word _fiq 58_pad: .word 0x12345678 /* now 16*4=64 */ 59#else 60_undefined_instruction: .word undefined_instruction 61_software_interrupt: .word software_interrupt 62_prefetch_abort: .word prefetch_abort 63_data_abort: .word data_abort 64_not_used: .word not_used 65_irq: .word irq 66_fiq: .word fiq 67_pad: .word 0x12345678 /* now 16*4=64 */ 68#endif /* CONFIG_SPL_BUILD */ 69 70 .balignl 16,0xdeadbeef 71 72 73/* 74 ************************************************************************* 75 * 76 * Startup Code (reset vector) 77 * 78 * do important init only if we don't start from RAM! 79 * relocate armboot to ram 80 * setup stack 81 * jump to second stage 82 * 83 ************************************************************************* 84 */ 85 86.globl _TEXT_BASE 87_TEXT_BASE: 88#ifdef CONFIG_SPL_BUILD 89 .word CONFIG_SPL_TEXT_BASE 90#else 91 .word CONFIG_SYS_TEXT_BASE 92#endif 93 94/* 95 * These are defined in the board-specific linker script. 96 * Subtracting _start from them lets the linker put their 97 * relative position in the executable instead of leaving 98 * them null. 99 */ 100.globl _bss_start_ofs 101_bss_start_ofs: 102 .word __bss_start - _start 103 104.globl _bss_end_ofs 105_bss_end_ofs: 106 .word __bss_end__ - _start 107 108.globl _end_ofs 109_end_ofs: 110 .word _end - _start 111 112#ifdef CONFIG_USE_IRQ 113/* IRQ stack memory (calculated at run-time) */ 114.globl IRQ_STACK_START 115IRQ_STACK_START: 116 .word 0x0badc0de 117 118/* IRQ stack memory (calculated at run-time) */ 119.globl FIQ_STACK_START 120FIQ_STACK_START: 121 .word 0x0badc0de 122#endif 123 124/* IRQ stack memory (calculated at run-time) + 8 bytes */ 125.globl IRQ_STACK_START_IN 126IRQ_STACK_START_IN: 127 .word 0x0badc0de 128 129/* 130 * the actual reset code 131 */ 132 133reset: 134 /* 135 * set the cpu to SVC32 mode 136 */ 137 mrs r0,cpsr 138 bic r0,r0,#0x1f 139 orr r0,r0,#0xd3 140 msr cpsr,r0 141 142 /* 143 * we do sys-critical inits only at reboot, 144 * not when booting from ram! 145 */ 146#ifndef CONFIG_SKIP_LOWLEVEL_INIT 147 bl cpu_init_crit 148#endif 149 150/* Set stackpointer in internal RAM to call board_init_f */ 151call_board_init_f: 152 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 153 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 154 ldr r0,=0x00000000 155 bl board_init_f 156 157/*------------------------------------------------------------------------------*/ 158 159/* 160 * void relocate_code (addr_sp, gd, addr_moni) 161 * 162 * This "function" does not return, instead it continues in RAM 163 * after relocating the monitor code. 164 * 165 */ 166 .globl relocate_code 167relocate_code: 168 mov r4, r0 /* save addr_sp */ 169 mov r5, r1 /* save addr of gd */ 170 mov r6, r2 /* save addr of destination */ 171 172 /* Set up the stack */ 173stack_setup: 174 mov sp, r4 175 176 adr r0, _start 177 cmp r0, r6 178 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 179 beq clear_bss /* skip relocation */ 180 mov r1, r6 /* r1 <- scratch for copy_loop */ 181 ldr r3, _bss_start_ofs 182 add r2, r0, r3 /* r2 <- source end address */ 183 184copy_loop: 185 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 186 stmia r1!, {r9-r10} /* copy to target address [r1] */ 187 cmp r0, r2 /* until source end address [r2] */ 188 blo copy_loop 189 190#ifndef CONFIG_SPL_BUILD 191 /* 192 * fix .rel.dyn relocations 193 */ 194 ldr r0, _TEXT_BASE /* r0 <- Text base */ 195 sub r9, r6, r0 /* r9 <- relocation offset */ 196 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 197 add r10, r10, r0 /* r10 <- sym table in FLASH */ 198 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 199 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 200 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 201 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 202fixloop: 203 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 204 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 205 ldr r1, [r2, #4] 206 and r7, r1, #0xff 207 cmp r7, #23 /* relative fixup? */ 208 beq fixrel 209 cmp r7, #2 /* absolute fixup? */ 210 beq fixabs 211 /* ignore unknown type of fixup */ 212 b fixnext 213fixabs: 214 /* absolute fix: set location to (offset) symbol value */ 215 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 216 add r1, r10, r1 /* r1 <- address of symbol in table */ 217 ldr r1, [r1, #4] /* r1 <- symbol value */ 218 add r1, r1, r9 /* r1 <- relocated sym addr */ 219 b fixnext 220fixrel: 221 /* relative fix: increase location by offset */ 222 ldr r1, [r0] 223 add r1, r1, r9 224fixnext: 225 str r1, [r0] 226 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 227 cmp r2, r3 228 blo fixloop 229#endif 230 231clear_bss: 232#ifndef CONFIG_SPL_BUILD 233 ldr r0, _bss_start_ofs 234 ldr r1, _bss_end_ofs 235 mov r4, r6 /* reloc addr */ 236 add r0, r0, r4 237 add r1, r1, r4 238 mov r2, #0x00000000 /* clear */ 239 240clbss_l:cmp r0, r1 /* clear loop... */ 241 bhs clbss_e /* if reached end of bss, exit */ 242 str r2, [r0] 243 add r0, r0, #4 244 b clbss_l 245clbss_e: 246 247 bl coloured_LED_init 248 bl red_led_on 249#endif 250 251/* 252 * We are done. Do not return, instead branch to second part of board 253 * initialization, now running from RAM. 254 */ 255 ldr r0, _board_init_r_ofs 256 adr r1, _start 257 add lr, r0, r1 258 add lr, lr, r9 259 /* setup parameters for board_init_r */ 260 mov r0, r5 /* gd_t */ 261 mov r1, r6 /* dest_addr */ 262 /* jump to it ... */ 263 mov pc, lr 264 265_board_init_r_ofs: 266 .word board_init_r - _start 267 268_rel_dyn_start_ofs: 269 .word __rel_dyn_start - _start 270_rel_dyn_end_ofs: 271 .word __rel_dyn_end - _start 272_dynsym_start_ofs: 273 .word __dynsym_start - _start 274 275/* 276 ************************************************************************* 277 * 278 * CPU_init_critical registers 279 * 280 * setup important registers 281 * setup memory timing 282 * 283 ************************************************************************* 284 */ 285 286cpu_init_crit: 287 288#if !defined(CONFIG_TEGRA) 289 mov ip, lr 290 /* 291 * before relocating, we have to setup RAM timing 292 * because memory timing is board-dependent, you will 293 * find a lowlevel_init.S in your board directory. 294 */ 295 bl lowlevel_init 296 mov lr, ip 297#endif 298 299 mov pc, lr 300 301 302#ifndef CONFIG_SPL_BUILD 303/* 304 ************************************************************************* 305 * 306 * Interrupt handling 307 * 308 ************************************************************************* 309 */ 310 311@ 312@ IRQ stack frame. 313@ 314#define S_FRAME_SIZE 72 315 316#define S_OLD_R0 68 317#define S_PSR 64 318#define S_PC 60 319#define S_LR 56 320#define S_SP 52 321 322#define S_IP 48 323#define S_FP 44 324#define S_R10 40 325#define S_R9 36 326#define S_R8 32 327#define S_R7 28 328#define S_R6 24 329#define S_R5 20 330#define S_R4 16 331#define S_R3 12 332#define S_R2 8 333#define S_R1 4 334#define S_R0 0 335 336#define MODE_SVC 0x13 337#define I_BIT 0x80 338 339/* 340 * use bad_save_user_regs for abort/prefetch/undef/swi ... 341 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 342 */ 343 344 .macro bad_save_user_regs 345 sub sp, sp, #S_FRAME_SIZE 346 stmia sp, {r0 - r12} @ Calling r0-r12 347 add r8, sp, #S_PC 348 349 ldr r2, IRQ_STACK_START_IN 350 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 351 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 352 353 add r5, sp, #S_SP 354 mov r1, lr 355 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 356 mov r0, sp 357 .endm 358 359 .macro irq_save_user_regs 360 sub sp, sp, #S_FRAME_SIZE 361 stmia sp, {r0 - r12} @ Calling r0-r12 362 add r8, sp, #S_PC 363 stmdb r8, {sp, lr}^ @ Calling SP, LR 364 str lr, [r8, #0] @ Save calling PC 365 mrs r6, spsr 366 str r6, [r8, #4] @ Save CPSR 367 str r0, [r8, #8] @ Save OLD_R0 368 mov r0, sp 369 .endm 370 371 .macro irq_restore_user_regs 372 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 373 mov r0, r0 374 ldr lr, [sp, #S_PC] @ Get PC 375 add sp, sp, #S_FRAME_SIZE 376 subs pc, lr, #4 @ return & move spsr_svc into cpsr 377 .endm 378 379 .macro get_bad_stack 380 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 381 382 str lr, [r13] @ save caller lr / spsr 383 mrs lr, spsr 384 str lr, [r13, #4] 385 386 mov r13, #MODE_SVC @ prepare SVC-Mode 387 msr spsr_c, r13 388 mov lr, pc 389 movs pc, lr 390 .endm 391 392 .macro get_irq_stack @ setup IRQ stack 393 ldr sp, IRQ_STACK_START 394 .endm 395 396 .macro get_fiq_stack @ setup FIQ stack 397 ldr sp, FIQ_STACK_START 398 .endm 399 400/* 401 * exception handlers 402 */ 403 .align 5 404undefined_instruction: 405 get_bad_stack 406 bad_save_user_regs 407 bl do_undefined_instruction 408 409 .align 5 410software_interrupt: 411 get_bad_stack 412 bad_save_user_regs 413 bl do_software_interrupt 414 415 .align 5 416prefetch_abort: 417 get_bad_stack 418 bad_save_user_regs 419 bl do_prefetch_abort 420 421 .align 5 422data_abort: 423 get_bad_stack 424 bad_save_user_regs 425 bl do_data_abort 426 427 .align 5 428not_used: 429 get_bad_stack 430 bad_save_user_regs 431 bl do_not_used 432 433#ifdef CONFIG_USE_IRQ 434 435 .align 5 436irq: 437 get_irq_stack 438 irq_save_user_regs 439 bl do_irq 440 irq_restore_user_regs 441 442 .align 5 443fiq: 444 get_fiq_stack 445 /* someone ought to write a more effiction fiq_save_user_regs */ 446 irq_save_user_regs 447 bl do_fiq 448 irq_restore_user_regs 449 450#else 451 452 .align 5 453irq: 454 get_bad_stack 455 bad_save_user_regs 456 bl do_irq 457 458 .align 5 459fiq: 460 get_bad_stack 461 bad_save_user_regs 462 bl do_fiq 463 464#endif 465#endif /* CONFIG_SPL_BUILD */ 466