xref: /openbmc/u-boot/arch/arm/cpu/arm720t/start.S (revision 1e52fea3) 
1/*
2 *  armboot - Startup Code for ARM720 CPU-core
3 *
4 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
5 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <asm-offsets.h>
27#include <config.h>
28#include <version.h>
29#include <asm/hardware.h>
30
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
41_start: b	reset
42	ldr	pc, _undefined_instruction
43	ldr	pc, _software_interrupt
44	ldr	pc, _prefetch_abort
45	ldr	pc, _data_abort
46#ifdef CONFIG_LPC2292
47	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
48#else
49	ldr	pc, _not_used
50#endif
51	ldr	pc, _irq
52	ldr	pc, _fiq
53
54_undefined_instruction: .word undefined_instruction
55_software_interrupt:	.word software_interrupt
56_prefetch_abort:	.word prefetch_abort
57_data_abort:		.word data_abort
58_not_used:		.word not_used
59_irq:			.word irq
60_fiq:			.word fiq
61
62	.balignl 16,0xdeadbeef
63
64
65/*
66 *************************************************************************
67 *
68 * Startup Code (reset vector)
69 *
70 * do important init only if we don't start from RAM!
71 * relocate armboot to ram
72 * setup stack
73 * jump to second stage
74 *
75 *************************************************************************
76 */
77
78.globl _TEXT_BASE
79_TEXT_BASE:
80	.word	CONFIG_SYS_TEXT_BASE
81
82/*
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
86 * them null.
87 */
88.globl _bss_start_ofs
89_bss_start_ofs:
90	.word __bss_start - _start
91
92.globl _bss_end_ofs
93_bss_end_ofs:
94	.word __bss_end__ - _start
95
96.globl _end_ofs
97_end_ofs:
98	.word _end - _start
99
100#ifdef CONFIG_USE_IRQ
101/* IRQ stack memory (calculated at run-time) */
102.globl IRQ_STACK_START
103IRQ_STACK_START:
104	.word	0x0badc0de
105
106/* IRQ stack memory (calculated at run-time) */
107.globl FIQ_STACK_START
108FIQ_STACK_START:
109	.word 0x0badc0de
110#endif
111
112/* IRQ stack memory (calculated at run-time) + 8 bytes */
113.globl IRQ_STACK_START_IN
114IRQ_STACK_START_IN:
115	.word	0x0badc0de
116
117/*
118 * the actual reset code
119 */
120
121reset:
122	/*
123	 * set the cpu to SVC32 mode
124	 */
125	mrs	r0,cpsr
126	bic	r0,r0,#0x1f
127	orr	r0,r0,#0xd3
128	msr	cpsr,r0
129
130	/*
131	 * we do sys-critical inits only at reboot,
132	 * not when booting from ram!
133	 */
134#ifndef CONFIG_SKIP_LOWLEVEL_INIT
135	bl	cpu_init_crit
136#endif
137
138#ifdef CONFIG_LPC2292
139	bl	lowlevel_init
140#endif
141
142/* Set stackpointer in internal RAM to call board_init_f */
143call_board_init_f:
144	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
145	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
146	ldr	r0,=0x00000000
147	bl	board_init_f
148
149/*------------------------------------------------------------------------------*/
150
151/*
152 * void relocate_code (addr_sp, gd, addr_moni)
153 *
154 * This "function" does not return, instead it continues in RAM
155 * after relocating the monitor code.
156 *
157 */
158	.globl	relocate_code
159relocate_code:
160	mov	r4, r0	/* save addr_sp */
161	mov	r5, r1	/* save addr of gd */
162	mov	r6, r2	/* save addr of destination */
163
164	/* Set up the stack						    */
165stack_setup:
166	mov	sp, r4
167
168	adr	r0, _start
169	cmp	r0, r6
170	beq	clear_bss		/* skip relocation */
171	mov	r1, r6			/* r1 <- scratch for copy_loop */
172	ldr	r3, _bss_start_ofs
173	add	r2, r0, r3		/* r2 <- source end address	    */
174
175copy_loop:
176	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
177	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
178	cmp	r0, r2			/* until source end address [r2]    */
179	blo	copy_loop
180
181#ifndef CONFIG_SPL_BUILD
182	/*
183	 * fix .rel.dyn relocations
184	 */
185	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
186	sub	r9, r6, r0		/* r9 <- relocation offset */
187	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
188	add	r10, r10, r0		/* r10 <- sym table in FLASH */
189	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
190	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
191	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
192	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
193fixloop:
194	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
195	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
196	ldr	r1, [r2, #4]
197	and	r7, r1, #0xff
198	cmp	r7, #23			/* relative fixup? */
199	beq	fixrel
200	cmp	r7, #2			/* absolute fixup? */
201	beq	fixabs
202	/* ignore unknown type of fixup */
203	b	fixnext
204fixabs:
205	/* absolute fix: set location to (offset) symbol value */
206	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
207	add	r1, r10, r1		/* r1 <- address of symbol in table */
208	ldr	r1, [r1, #4]		/* r1 <- symbol value */
209	add	r1, r1, r9		/* r1 <- relocated sym addr */
210	b	fixnext
211fixrel:
212	/* relative fix: increase location by offset */
213	ldr	r1, [r0]
214	add	r1, r1, r9
215fixnext:
216	str	r1, [r0]
217	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
218	cmp	r2, r3
219	blo	fixloop
220#endif
221
222clear_bss:
223#ifndef CONFIG_SPL_BUILD
224	ldr	r0, _bss_start_ofs
225	ldr	r1, _bss_end_ofs
226	mov	r4, r6			/* reloc addr */
227	add	r0, r0, r4
228	add	r1, r1, r4
229	mov	r2, #0x00000000		/* clear			    */
230
231clbss_l:str	r2, [r0]		/* clear loop...		    */
232	add	r0, r0, #4
233	cmp	r0, r1
234	bne	clbss_l
235
236	bl coloured_LED_init
237	bl red_led_on
238#endif
239
240/*
241 * We are done. Do not return, instead branch to second part of board
242 * initialization, now running from RAM.
243 */
244	ldr	r0, _board_init_r_ofs
245	adr	r1, _start
246	add	lr, r0, r1
247	add	lr, lr, r9
248	/* setup parameters for board_init_r */
249	mov	r0, r5		/* gd_t */
250	mov	r1, r6		/* dest_addr */
251	/* jump to it ... */
252	mov	pc, lr
253
254_board_init_r_ofs:
255	.word board_init_r - _start
256
257_rel_dyn_start_ofs:
258	.word __rel_dyn_start - _start
259_rel_dyn_end_ofs:
260	.word __rel_dyn_end - _start
261_dynsym_start_ofs:
262	.word __dynsym_start - _start
263
264/*
265 *************************************************************************
266 *
267 * CPU_init_critical registers
268 *
269 * setup important registers
270 * setup memory timing
271 *
272 *************************************************************************
273 */
274
275#if defined(CONFIG_LPC2292)
276PLLCFG_ADR:	.word	PLLCFG
277PLLFEED_ADR:	.word	PLLFEED
278PLLCON_ADR:	.word	PLLCON
279PLLSTAT_ADR:	.word	PLLSTAT
280VPBDIV_ADR:	.word	VPBDIV
281MEMMAP_ADR:	.word	MEMMAP
282
283#endif
284
285cpu_init_crit:
286#if defined(CONFIG_NETARM)
287	/*
288	 * prior to software reset : need to set pin PORTC4 to be *HRESET
289	 */
290	ldr	r0, =NETARM_GEN_MODULE_BASE
291	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
292			NETARM_GEN_PORT_DIR(0x10))
293	str	r1, [r0, #+NETARM_GEN_PORTC]
294	/*
295	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
296	 *		    for an explanation of this process
297	 */
298	ldr	r0, =NETARM_GEN_MODULE_BASE
299	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
300	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
301	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
302	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
303	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
304	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
305	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
306	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
307	/*
308	 * setup PLL and System Config
309	 */
310	ldr	r0, =NETARM_GEN_MODULE_BASE
311
312	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
313			NETARM_GEN_SYS_CFG_BUSFULL | \
314			NETARM_GEN_SYS_CFG_USER_EN | \
315			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
316			NETARM_GEN_SYS_CFG_BUSARB_INT | \
317			NETARM_GEN_SYS_CFG_BUSMON_EN )
318
319	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
320
321#ifndef CONFIG_NETARM_PLL_BYPASS
322	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
323			NETARM_GEN_PLL_CTL_POLTST_DEF | \
324			NETARM_GEN_PLL_CTL_INDIV(1) | \
325			NETARM_GEN_PLL_CTL_ICP_DEF | \
326			NETARM_GEN_PLL_CTL_OUTDIV(2) )
327	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
328#endif
329
330	/*
331	 * mask all IRQs by clearing all bits in the INTMRs
332	 */
333	mov	r1, #0
334	ldr	r0, =NETARM_GEN_MODULE_BASE
335	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
336
337#elif defined(CONFIG_S3C4510B)
338
339	/*
340	 * Mask off all IRQ sources
341	 */
342	ldr	r1, =REG_INTMASK
343	ldr	r0, =0x3FFFFF
344	str	r0, [r1]
345
346	/*
347	 * Disable Cache
348	 */
349	ldr r0, =REG_SYSCFG
350	ldr r1, =0x83ffffa0	/* cache-disabled  */
351	str r1, [r0]
352
353#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
354	/* No specific initialisation for IntegratorAP/CM720T as yet */
355#elif defined(CONFIG_LPC2292)
356	/* Set-up PLL */
357	mov	r3, #0xAA
358	mov	r4, #0x55
359	/* First disconnect and disable the PLL */
360	ldr	r0, PLLCON_ADR
361	mov	r1, #0x00
362	str	r1, [r0]
363	ldr	r0, PLLFEED_ADR /* start feed sequence */
364	str	r3, [r0]
365	str	r4, [r0]	/* feed sequence done */
366	/* Set new M and P values */
367	ldr	r0, PLLCFG_ADR
368	mov	r1, #0x23	/* M=4 and P=2 */
369	str	r1, [r0]
370	ldr	r0, PLLFEED_ADR /* start feed sequence */
371	str	r3, [r0]
372	str	r4, [r0]	/* feed sequence done */
373	/* Then enable the PLL */
374	ldr	r0, PLLCON_ADR
375	mov	r1, #0x01	/* PLL enable bit */
376	str	r1, [r0]
377	ldr	r0, PLLFEED_ADR /* start feed sequence */
378	str	r3, [r0]
379	str	r4, [r0]	/* feed sequence done */
380	/* Wait for the lock */
381	ldr	r0, PLLSTAT_ADR
382	mov	r1, #0x400	/* lock bit */
383lock_loop:
384	ldr	r2, [r0]
385	and	r2, r1, r2
386	cmp	r2, #0
387	beq	lock_loop
388	/* And finally connect the PLL */
389	ldr	r0, PLLCON_ADR
390	mov	r1, #0x03	/* PLL enable bit and connect bit */
391	str	r1, [r0]
392	ldr	r0, PLLFEED_ADR /* start feed sequence */
393	str	r3, [r0]
394	str	r4, [r0]	/* feed sequence done */
395	/* Set-up VPBDIV register */
396	ldr	r0, VPBDIV_ADR
397	mov	r1, #0x01	/* VPB clock is same as process clock */
398	str	r1, [r0]
399#else
400#error No cpu_init_crit() defined for current CPU type
401#endif
402
403#ifdef CONFIG_ARM7_REVD
404	/* set clock speed */
405	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
406	/* !!! not doing DRAM refresh properly! */
407	ldr	r0, SYSCON3
408	ldr	r1, [r0]
409	bic	r1, r1, #CLKCTL
410	orr	r1, r1, #CLKCTL_36
411	str	r1, [r0]
412#endif
413
414#ifndef CONFIG_LPC2292
415	mov	ip, lr
416	/*
417	 * before relocating, we have to setup RAM timing
418	 * because memory timing is board-dependent, you will
419	 * find a lowlevel_init.S in your board directory.
420	 */
421	bl	lowlevel_init
422	mov	lr, ip
423#endif
424
425	mov	pc, lr
426
427
428/*
429 *************************************************************************
430 *
431 * Interrupt handling
432 *
433 *************************************************************************
434 */
435
436@
437@ IRQ stack frame.
438@
439#define S_FRAME_SIZE	72
440
441#define S_OLD_R0	68
442#define S_PSR		64
443#define S_PC		60
444#define S_LR		56
445#define S_SP		52
446
447#define S_IP		48
448#define S_FP		44
449#define S_R10		40
450#define S_R9		36
451#define S_R8		32
452#define S_R7		28
453#define S_R6		24
454#define S_R5		20
455#define S_R4		16
456#define S_R3		12
457#define S_R2		8
458#define S_R1		4
459#define S_R0		0
460
461#define MODE_SVC 0x13
462#define I_BIT	 0x80
463
464/*
465 * use bad_save_user_regs for abort/prefetch/undef/swi ...
466 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
467 */
468
469	.macro	bad_save_user_regs
470	sub	sp, sp, #S_FRAME_SIZE
471	stmia	sp, {r0 - r12}			@ Calling r0-r12
472	add	r8, sp, #S_PC
473
474	ldr	r2, IRQ_STACK_START_IN
475	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
476	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
477
478	add	r5, sp, #S_SP
479	mov	r1, lr
480	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
481	mov	r0, sp
482	.endm
483
484	.macro	irq_save_user_regs
485	sub	sp, sp, #S_FRAME_SIZE
486	stmia	sp, {r0 - r12}			@ Calling r0-r12
487	add	r8, sp, #S_PC
488	stmdb	r8, {sp, lr}^			@ Calling SP, LR
489	str	lr, [r8, #0]			@ Save calling PC
490	mrs	r6, spsr
491	str	r6, [r8, #4]			@ Save CPSR
492	str	r0, [r8, #8]			@ Save OLD_R0
493	mov	r0, sp
494	.endm
495
496	.macro	irq_restore_user_regs
497	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
498	mov	r0, r0
499	ldr	lr, [sp, #S_PC]			@ Get PC
500	add	sp, sp, #S_FRAME_SIZE
501	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
502	.endm
503
504	.macro get_bad_stack
505	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
506
507	str	lr, [r13]			@ save caller lr / spsr
508	mrs	lr, spsr
509	str	lr, [r13, #4]
510
511	mov	r13, #MODE_SVC			@ prepare SVC-Mode
512	msr	spsr_c, r13
513	mov	lr, pc
514	movs	pc, lr
515	.endm
516
517	.macro get_irq_stack			@ setup IRQ stack
518	ldr	sp, IRQ_STACK_START
519	.endm
520
521	.macro get_fiq_stack			@ setup FIQ stack
522	ldr	sp, FIQ_STACK_START
523	.endm
524
525/*
526 * exception handlers
527 */
528	.align	5
529undefined_instruction:
530	get_bad_stack
531	bad_save_user_regs
532	bl	do_undefined_instruction
533
534	.align	5
535software_interrupt:
536	get_bad_stack
537	bad_save_user_regs
538	bl	do_software_interrupt
539
540	.align	5
541prefetch_abort:
542	get_bad_stack
543	bad_save_user_regs
544	bl	do_prefetch_abort
545
546	.align	5
547data_abort:
548	get_bad_stack
549	bad_save_user_regs
550	bl	do_data_abort
551
552	.align	5
553not_used:
554	get_bad_stack
555	bad_save_user_regs
556	bl	do_not_used
557
558#ifdef CONFIG_USE_IRQ
559
560	.align	5
561irq:
562	get_irq_stack
563	irq_save_user_regs
564	bl	do_irq
565	irq_restore_user_regs
566
567	.align	5
568fiq:
569	get_fiq_stack
570	/* someone ought to write a more effiction fiq_save_user_regs */
571	irq_save_user_regs
572	bl	do_fiq
573	irq_restore_user_regs
574
575#else
576
577	.align	5
578irq:
579	get_bad_stack
580	bad_save_user_regs
581	bl	do_irq
582
583	.align	5
584fiq:
585	get_bad_stack
586	bad_save_user_regs
587	bl	do_fiq
588
589#endif
590
591#if defined(CONFIG_NETARM)
592	.align	5
593.globl reset_cpu
594reset_cpu:
595	ldr	r1, =NETARM_MEM_MODULE_BASE
596	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
597	ldr	r1, =0xFFFFF000
598	and	r0, r1, r0
599	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
600	add	r0, r1, r0
601	ldr	r4, =NETARM_GEN_MODULE_BASE
602	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
603	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
604	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
605	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
606	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
607	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
608	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
609	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
610	mov	pc, r0
611#elif defined(CONFIG_S3C4510B)
612/* Nothing done here as reseting the CPU is board specific, depending
613 * on external peripherals such as watchdog timers, etc. */
614#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
615	/* No specific reset actions for IntegratorAP/CM720T as yet */
616#elif defined(CONFIG_LPC2292)
617	.align	5
618.globl reset_cpu
619reset_cpu:
620	mov	pc, r0
621#else
622#error No reset_cpu() defined for current CPU type
623#endif
624