1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <asm-offsets.h> 34#include <config.h> 35#include <version.h> 36#ifdef CONFIG_ENABLE_MMU 37#include <asm/proc/domain.h> 38#endif 39 40#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) 41#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 42#endif 43 44/* 45 ************************************************************************* 46 * 47 * Jump vector table as in table 3.1 in [1] 48 * 49 ************************************************************************* 50 */ 51 52.globl _start 53_start: b reset 54#ifndef CONFIG_NAND_SPL 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: 64 .word undefined_instruction 65_software_interrupt: 66 .word software_interrupt 67_prefetch_abort: 68 .word prefetch_abort 69_data_abort: 70 .word data_abort 71_not_used: 72 .word not_used 73_irq: 74 .word irq 75_fiq: 76 .word fiq 77_pad: 78 .word 0x12345678 /* now 16*4=64 */ 79#else 80 . = _start + 64 81#endif 82 83.global _end_vect 84_end_vect: 85 .balignl 16,0xdeadbeef 86/* 87 ************************************************************************* 88 * 89 * Startup Code (reset vector) 90 * 91 * do important init only if we don't start from memory! 92 * setup Memory and board specific bits prior to relocation. 93 * relocate armboot to ram 94 * setup stack 95 * 96 ************************************************************************* 97 */ 98 99.globl _TEXT_BASE 100_TEXT_BASE: 101 .word CONFIG_SYS_TEXT_BASE 102 103/* 104 * Below variable is very important because we use MMU in U-Boot. 105 * Without it, we cannot run code correctly before MMU is ON. 106 * by scsuh. 107 */ 108_TEXT_PHY_BASE: 109 .word CONFIG_SYS_PHY_UBOOT_BASE 110 111/* 112 * These are defined in the board-specific linker script. 113 * Subtracting _start from them lets the linker put their 114 * relative position in the executable instead of leaving 115 * them null. 116 */ 117 118.globl _bss_start_ofs 119_bss_start_ofs: 120 .word __bss_start - _start 121 122.globl _bss_end_ofs 123_bss_end_ofs: 124 .word _end - _start 125 126/* IRQ stack memory (calculated at run-time) + 8 bytes */ 127.globl IRQ_STACK_START_IN 128IRQ_STACK_START_IN: 129 .word 0x0badc0de 130 131/* 132 * the actual reset code 133 */ 134 135reset: 136 /* 137 * set the cpu to SVC32 mode 138 */ 139 mrs r0, cpsr 140 bic r0, r0, #0x3f 141 orr r0, r0, #0xd3 142 msr cpsr, r0 143 144/* 145 ************************************************************************* 146 * 147 * CPU_init_critical registers 148 * 149 * setup important registers 150 * setup memory timing 151 * 152 ************************************************************************* 153 */ 154 /* 155 * we do sys-critical inits only at reboot, 156 * not when booting from ram! 157 */ 158cpu_init_crit: 159 /* 160 * When booting from NAND - it has definitely been a reset, so, no need 161 * to flush caches and disable the MMU 162 */ 163#ifndef CONFIG_NAND_SPL 164 /* 165 * flush v4 I/D caches 166 */ 167 mov r0, #0 168 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 169 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 170 171 /* 172 * disable MMU stuff and caches 173 */ 174 mrc p15, 0, r0, c1, c0, 0 175 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 176 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 177 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 178 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 179 180 /* Prepare to disable the MMU */ 181 adr r2, mmu_disable_phys 182 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 183 b mmu_disable 184 185 .align 5 186 /* Run in a single cache-line */ 187mmu_disable: 188 mcr p15, 0, r0, c1, c0, 0 189 nop 190 nop 191 mov pc, r2 192mmu_disable_phys: 193 194#ifdef CONFIG_DISABLE_TCM 195 /* 196 * Disable the TCMs 197 */ 198 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 199 cmp r0, #0 200 beq skip_tcmdisable 201 mov r1, #0 202 mov r2, #1 203 tst r0, r2 204 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 205 tst r0, r2, LSL #16 206 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 207skip_tcmdisable: 208#endif 209#endif 210 211#ifdef CONFIG_PERIPORT_REMAP 212 /* Peri port setup */ 213 ldr r0, =CONFIG_PERIPORT_BASE 214 orr r0, r0, #CONFIG_PERIPORT_SIZE 215 mcr p15,0,r0,c15,c2,4 216#endif 217 218 /* 219 * Go setup Memory and board specific bits prior to relocation. 220 */ 221 bl lowlevel_init /* go setup pll,mux,memory */ 222 223/* Set stackpointer in internal RAM to call board_init_f */ 224call_board_init_f: 225 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 226 ldr r0,=0x00000000 227 bl board_init_f 228 229/*------------------------------------------------------------------------------*/ 230 231/* 232 * void relocate_code (addr_sp, gd, addr_moni) 233 * 234 * This "function" does not return, instead it continues in RAM 235 * after relocating the monitor code. 236 * 237 */ 238 .globl relocate_code 239relocate_code: 240 mov r4, r0 /* save addr_sp */ 241 mov r5, r1 /* save addr of gd */ 242 mov r6, r2 /* save addr of destination */ 243 mov r7, r2 /* save addr of destination */ 244 245 /* Set up the stack */ 246stack_setup: 247 mov sp, r4 248 249 adr r0, _start 250 ldr r2, _TEXT_BASE 251 ldr r3, _bss_start_ofs 252 add r2, r0, r3 /* r2 <- source end address */ 253 cmp r0, r6 254 beq clear_bss 255 256copy_loop: 257 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 258 stmia r6!, {r9-r10} /* copy to target address [r1] */ 259 cmp r0, r2 /* until source end address [r2] */ 260 blo copy_loop 261 262#ifndef CONFIG_PRELOADER 263 /* 264 * fix .rel.dyn relocations 265 */ 266 ldr r0, _TEXT_BASE /* r0 <- Text base */ 267 sub r9, r7, r0 /* r9 <- relocation offset */ 268 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 269 add r10, r10, r0 /* r10 <- sym table in FLASH */ 270 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 271 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 272 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 273 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 274fixloop: 275 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 276 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 277 ldr r1, [r2, #4] 278 and r8, r1, #0xff 279 cmp r8, #23 /* relative fixup? */ 280 beq fixrel 281 cmp r8, #2 /* absolute fixup? */ 282 beq fixabs 283 /* ignore unknown type of fixup */ 284 b fixnext 285fixabs: 286 /* absolute fix: set location to (offset) symbol value */ 287 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 288 add r1, r10, r1 /* r1 <- address of symbol in table */ 289 ldr r1, [r1, #4] /* r1 <- symbol value */ 290 add r1, r9 /* r1 <- relocated sym addr */ 291 b fixnext 292fixrel: 293 /* relative fix: increase location by offset */ 294 ldr r1, [r0] 295 add r1, r1, r9 296fixnext: 297 str r1, [r0] 298 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 299 cmp r2, r3 300 blo fixloop 301#endif 302 303#ifdef CONFIG_ENABLE_MMU 304enable_mmu: 305 /* enable domain access */ 306 ldr r5, =0x0000ffff 307 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ 308 309 /* Set the TTB register */ 310 ldr r0, _mmu_table_base 311 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE 312 ldr r2, =0xfff00000 313 bic r0, r0, r2 314 orr r1, r0, r1 315 mcr p15, 0, r1, c2, c0, 0 316 317 /* Enable the MMU */ 318 mrc p15, 0, r0, c1, c0, 0 319 orr r0, r0, #1 /* Set CR_M to enable MMU */ 320 321 /* Prepare to enable the MMU */ 322 adr r1, skip_hw_init 323 and r1, r1, #0x3fc 324 ldr r2, _TEXT_BASE 325 ldr r3, =0xfff00000 326 and r2, r2, r3 327 orr r2, r2, r1 328 b mmu_enable 329 330 .align 5 331 /* Run in a single cache-line */ 332mmu_enable: 333 334 mcr p15, 0, r0, c1, c0, 0 335 nop 336 nop 337 mov pc, r2 338skip_hw_init: 339#endif 340 341clear_bss: 342#ifndef CONFIG_PRELOADER 343 ldr r0, _bss_start_ofs 344 ldr r1, _bss_end_ofs 345 ldr r3, _TEXT_BASE /* Text base */ 346 mov r4, r7 /* reloc addr */ 347 add r0, r0, r4 348 add r1, r1, r4 349 mov r2, #0x00000000 /* clear */ 350 351clbss_l:str r2, [r0] /* clear loop... */ 352 add r0, r0, #4 353 cmp r0, r1 354 bne clbss_l 355 356 bl coloured_LED_init 357 bl red_LED_on 358#endif 359 360/* 361 * We are done. Do not return, instead branch to second part of board 362 * initialization, now running from RAM. 363 */ 364#ifdef CONFIG_NAND_SPL 365 ldr pc, _nand_boot 366 367_nand_boot: .word nand_boot 368#else 369 ldr r0, _board_init_r_ofs 370 adr r1, _start 371 add lr, r0, r1 372 add lr, lr, r9 373 /* setup parameters for board_init_r */ 374 mov r0, r5 /* gd_t */ 375 mov r1, r7 /* dest_addr */ 376 /* jump to it ... */ 377 mov pc, lr 378 379_board_init_r_ofs: 380 .word board_init_r - _start 381#endif 382 383_rel_dyn_start_ofs: 384 .word __rel_dyn_start - _start 385_rel_dyn_end_ofs: 386 .word __rel_dyn_end - _start 387_dynsym_start_ofs: 388 .word __dynsym_start - _start 389 390#ifdef CONFIG_ENABLE_MMU 391_mmu_table_base: 392 .word mmu_table 393#endif 394 395#ifndef CONFIG_NAND_SPL 396/* 397 * we assume that cache operation is done before. (eg. cleanup_before_linux()) 398 * actually, we don't need to do anything about cache if not use d-cache in 399 * U-Boot. So, in this function we clean only MMU. by scsuh 400 * 401 * void theLastJump(void *kernel, int arch_num, uint boot_params); 402 */ 403#ifdef CONFIG_ENABLE_MMU 404 .globl theLastJump 405theLastJump: 406 mov r9, r0 407 ldr r3, =0xfff00000 408 ldr r4, _TEXT_PHY_BASE 409 adr r5, phy_last_jump 410 bic r5, r5, r3 411 orr r5, r5, r4 412 mov pc, r5 413phy_last_jump: 414 /* 415 * disable MMU stuff 416 */ 417 mrc p15, 0, r0, c1, c0, 0 418 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 419 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 420 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 421 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 422 mcr p15, 0, r0, c1, c0, 0 423 424 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 425 426 mov r0, #0 427 mov pc, r9 428#endif 429 430 431/* 432 ************************************************************************* 433 * 434 * Interrupt handling 435 * 436 ************************************************************************* 437 */ 438@ 439@ IRQ stack frame. 440@ 441#define S_FRAME_SIZE 72 442 443#define S_OLD_R0 68 444#define S_PSR 64 445#define S_PC 60 446#define S_LR 56 447#define S_SP 52 448 449#define S_IP 48 450#define S_FP 44 451#define S_R10 40 452#define S_R9 36 453#define S_R8 32 454#define S_R7 28 455#define S_R6 24 456#define S_R5 20 457#define S_R4 16 458#define S_R3 12 459#define S_R2 8 460#define S_R1 4 461#define S_R0 0 462 463#define MODE_SVC 0x13 464#define I_BIT 0x80 465 466/* 467 * use bad_save_user_regs for abort/prefetch/undef/swi ... 468 */ 469 470 .macro bad_save_user_regs 471 /* carve out a frame on current user stack */ 472 sub sp, sp, #S_FRAME_SIZE 473 /* Save user registers (now in svc mode) r0-r12 */ 474 stmia sp, {r0 - r12} 475 476 ldr r2, IRQ_STACK_START_IN 477 /* get values for "aborted" pc and cpsr (into parm regs) */ 478 ldmia r2, {r2 - r3} 479 /* grab pointer to old stack */ 480 add r0, sp, #S_FRAME_SIZE 481 482 add r5, sp, #S_SP 483 mov r1, lr 484 /* save sp_SVC, lr_SVC, pc, cpsr */ 485 stmia r5, {r0 - r3} 486 /* save current stack into r0 (param register) */ 487 mov r0, sp 488 .endm 489 490 .macro get_bad_stack 491 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 492 493 /* save caller lr in position 0 of saved stack */ 494 str lr, [r13] 495 /* get the spsr */ 496 mrs lr, spsr 497 /* save spsr in position 1 of saved stack */ 498 str lr, [r13, #4] 499 500 /* prepare SVC-Mode */ 501 mov r13, #MODE_SVC 502 @ msr spsr_c, r13 503 /* switch modes, make sure moves will execute */ 504 msr spsr, r13 505 /* capture return pc */ 506 mov lr, pc 507 /* jump to next instruction & switch modes. */ 508 movs pc, lr 509 .endm 510 511 .macro get_bad_stack_swi 512 /* space on current stack for scratch reg. */ 513 sub r13, r13, #4 514 /* save R0's value. */ 515 str r0, [r13] 516 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 517 /* save caller lr in position 0 of saved stack */ 518 str lr, [r0] 519 /* get the spsr */ 520 mrs r0, spsr 521 /* save spsr in position 1 of saved stack */ 522 str lr, [r0, #4] 523 /* restore r0 */ 524 ldr r0, [r13] 525 /* pop stack entry */ 526 add r13, r13, #4 527 .endm 528 529/* 530 * exception handlers 531 */ 532 .align 5 533undefined_instruction: 534 get_bad_stack 535 bad_save_user_regs 536 bl do_undefined_instruction 537 538 .align 5 539software_interrupt: 540 get_bad_stack_swi 541 bad_save_user_regs 542 bl do_software_interrupt 543 544 .align 5 545prefetch_abort: 546 get_bad_stack 547 bad_save_user_regs 548 bl do_prefetch_abort 549 550 .align 5 551data_abort: 552 get_bad_stack 553 bad_save_user_regs 554 bl do_data_abort 555 556 .align 5 557not_used: 558 get_bad_stack 559 bad_save_user_regs 560 bl do_not_used 561 562 .align 5 563irq: 564 get_bad_stack 565 bad_save_user_regs 566 bl do_irq 567 568 .align 5 569fiq: 570 get_bad_stack 571 bad_save_user_regs 572 bl do_fiq 573#endif /* CONFIG_NAND_SPL */ 574