1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * armboot - Startup Code for ARM1176 CPU-core 4 * 5 * Copyright (c) 2007 Samsung Electronics 6 * 7 * Copyright (C) 2008 8 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 9 * 10 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 11 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 12 * jsgood (jsgood.yang@samsung.com) 13 * Base codes by scsuh (sc.suh) 14 */ 15 16#include <asm-offsets.h> 17#include <config.h> 18#include <linux/linkage.h> 19 20#ifndef CONFIG_SYS_PHY_UBOOT_BASE 21#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 22#endif 23 24/* 25 ************************************************************************* 26 * 27 * Startup Code (reset vector) 28 * 29 * do important init only if we don't start from memory! 30 * setup Memory and board specific bits prior to relocation. 31 * relocate armboot to ram 32 * setup stack 33 * 34 ************************************************************************* 35 */ 36 37 .globl reset 38 39reset: 40 /* Allow the board to save important registers */ 41 b save_boot_params 42.globl save_boot_params_ret 43save_boot_params_ret: 44 45 /* 46 * set the cpu to SVC32 mode 47 */ 48 mrs r0, cpsr 49 bic r0, r0, #0x3f 50 orr r0, r0, #0xd3 51 msr cpsr, r0 52 53/* 54 ************************************************************************* 55 * 56 * CPU_init_critical registers 57 * 58 * setup important registers 59 * setup memory timing 60 * 61 ************************************************************************* 62 */ 63 /* 64 * we do sys-critical inits only at reboot, 65 * not when booting from ram! 66 */ 67cpu_init_crit: 68 /* 69 * When booting from NAND - it has definitely been a reset, so, no need 70 * to flush caches and disable the MMU 71 */ 72#ifndef CONFIG_SPL_BUILD 73 /* 74 * flush v4 I/D caches 75 */ 76 mov r0, #0 77 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 78 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 79 80 /* 81 * disable MMU stuff and caches 82 */ 83 mrc p15, 0, r0, c1, c0, 0 84 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 85 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 86 orr r0, r0, #0x00000002 @ set bit 1 (A) Align 87 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 88 89 /* Prepare to disable the MMU */ 90 adr r2, mmu_disable_phys 91 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 92 b mmu_disable 93 94 .align 5 95 /* Run in a single cache-line */ 96mmu_disable: 97 mcr p15, 0, r0, c1, c0, 0 98 nop 99 nop 100 mov pc, r2 101mmu_disable_phys: 102 103#endif 104 105 /* 106 * Go setup Memory and board specific bits prior to relocation. 107 */ 108 bl lowlevel_init /* go setup pll,mux,memory */ 109 110 bl _main 111 112/*------------------------------------------------------------------------------*/ 113 114 .globl c_runtime_cpu_setup 115c_runtime_cpu_setup: 116 117 mov pc, lr 118 119WEAK(save_boot_params) 120 b save_boot_params_ret /* back to my caller */ 121ENDPROC(save_boot_params) 122