1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 * 11 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 12 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 13 * jsgood (jsgood.yang@samsung.com) 14 * Base codes by scsuh (sc.suh) 15 */ 16 17#include <asm-offsets.h> 18#include <config.h> 19 20#ifndef CONFIG_SYS_PHY_UBOOT_BASE 21#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 22#endif 23 24/* 25 ************************************************************************* 26 * 27 * Startup Code (reset vector) 28 * 29 * do important init only if we don't start from memory! 30 * setup Memory and board specific bits prior to relocation. 31 * relocate armboot to ram 32 * setup stack 33 * 34 ************************************************************************* 35 */ 36 37 .globl reset 38 39reset: 40 /* 41 * set the cpu to SVC32 mode 42 */ 43 mrs r0, cpsr 44 bic r0, r0, #0x3f 45 orr r0, r0, #0xd3 46 msr cpsr, r0 47 48/* 49 ************************************************************************* 50 * 51 * CPU_init_critical registers 52 * 53 * setup important registers 54 * setup memory timing 55 * 56 ************************************************************************* 57 */ 58 /* 59 * we do sys-critical inits only at reboot, 60 * not when booting from ram! 61 */ 62cpu_init_crit: 63 /* 64 * When booting from NAND - it has definitely been a reset, so, no need 65 * to flush caches and disable the MMU 66 */ 67#ifndef CONFIG_SPL_BUILD 68 /* 69 * flush v4 I/D caches 70 */ 71 mov r0, #0 72 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 73 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 74 75 /* 76 * disable MMU stuff and caches 77 */ 78 mrc p15, 0, r0, c1, c0, 0 79 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 80 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 81 orr r0, r0, #0x00000002 @ set bit 1 (A) Align 82 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 83 84 /* Prepare to disable the MMU */ 85 adr r2, mmu_disable_phys 86 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 87 b mmu_disable 88 89 .align 5 90 /* Run in a single cache-line */ 91mmu_disable: 92 mcr p15, 0, r0, c1, c0, 0 93 nop 94 nop 95 mov pc, r2 96mmu_disable_phys: 97 98#endif 99 100 /* 101 * Go setup Memory and board specific bits prior to relocation. 102 */ 103 bl lowlevel_init /* go setup pll,mux,memory */ 104 105 bl _main 106 107/*------------------------------------------------------------------------------*/ 108 109 .globl c_runtime_cpu_setup 110c_runtime_cpu_setup: 111 112 mov pc, lr 113