1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <asm-offsets.h> 34#include <config.h> 35#include <version.h> 36 37#ifndef CONFIG_SYS_PHY_UBOOT_BASE 38#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 39#endif 40 41/* 42 ************************************************************************* 43 * 44 * Jump vector table as in table 3.1 in [1] 45 * 46 ************************************************************************* 47 */ 48 49.globl _start 50_start: b reset 51#ifndef CONFIG_SPL_BUILD 52 ldr pc, _undefined_instruction 53 ldr pc, _software_interrupt 54 ldr pc, _prefetch_abort 55 ldr pc, _data_abort 56 ldr pc, _not_used 57 ldr pc, _irq 58 ldr pc, _fiq 59 60_undefined_instruction: 61 .word undefined_instruction 62_software_interrupt: 63 .word software_interrupt 64_prefetch_abort: 65 .word prefetch_abort 66_data_abort: 67 .word data_abort 68_not_used: 69 .word not_used 70_irq: 71 .word irq 72_fiq: 73 .word fiq 74_pad: 75 .word 0x12345678 /* now 16*4=64 */ 76#else 77 . = _start + 64 78#endif 79 80.global _end_vect 81_end_vect: 82 .balignl 16,0xdeadbeef 83/* 84 ************************************************************************* 85 * 86 * Startup Code (reset vector) 87 * 88 * do important init only if we don't start from memory! 89 * setup Memory and board specific bits prior to relocation. 90 * relocate armboot to ram 91 * setup stack 92 * 93 ************************************************************************* 94 */ 95 96.globl _TEXT_BASE 97_TEXT_BASE: 98#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 99 .word CONFIG_SPL_TEXT_BASE 100#else 101 .word CONFIG_SYS_TEXT_BASE 102#endif 103 104/* 105 * These are defined in the board-specific linker script. 106 * Subtracting _start from them lets the linker put their 107 * relative position in the executable instead of leaving 108 * them null. 109 */ 110 111.globl _bss_start_ofs 112_bss_start_ofs: 113 .word __bss_start - _start 114 115.globl _bss_end_ofs 116_bss_end_ofs: 117 .word __bss_end - _start 118 119.globl _end_ofs 120_end_ofs: 121 .word _end - _start 122 123/* IRQ stack memory (calculated at run-time) + 8 bytes */ 124.globl IRQ_STACK_START_IN 125IRQ_STACK_START_IN: 126 .word 0x0badc0de 127 128/* 129 * the actual reset code 130 */ 131 132reset: 133 /* 134 * set the cpu to SVC32 mode 135 */ 136 mrs r0, cpsr 137 bic r0, r0, #0x3f 138 orr r0, r0, #0xd3 139 msr cpsr, r0 140 141/* 142 ************************************************************************* 143 * 144 * CPU_init_critical registers 145 * 146 * setup important registers 147 * setup memory timing 148 * 149 ************************************************************************* 150 */ 151 /* 152 * we do sys-critical inits only at reboot, 153 * not when booting from ram! 154 */ 155cpu_init_crit: 156 /* 157 * When booting from NAND - it has definitely been a reset, so, no need 158 * to flush caches and disable the MMU 159 */ 160#ifndef CONFIG_SPL_BUILD 161 /* 162 * flush v4 I/D caches 163 */ 164 mov r0, #0 165 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 166 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 167 168 /* 169 * disable MMU stuff and caches 170 */ 171 mrc p15, 0, r0, c1, c0, 0 172 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 173 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 174 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 175 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 176 177 /* Prepare to disable the MMU */ 178 adr r2, mmu_disable_phys 179 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 180 b mmu_disable 181 182 .align 5 183 /* Run in a single cache-line */ 184mmu_disable: 185 mcr p15, 0, r0, c1, c0, 0 186 nop 187 nop 188 mov pc, r2 189mmu_disable_phys: 190 191#ifdef CONFIG_DISABLE_TCM 192 /* 193 * Disable the TCMs 194 */ 195 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 196 cmp r0, #0 197 beq skip_tcmdisable 198 mov r1, #0 199 mov r2, #1 200 tst r0, r2 201 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 202 tst r0, r2, LSL #16 203 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 204skip_tcmdisable: 205#endif 206#endif 207 208#ifdef CONFIG_PERIPORT_REMAP 209 /* Peri port setup */ 210 ldr r0, =CONFIG_PERIPORT_BASE 211 orr r0, r0, #CONFIG_PERIPORT_SIZE 212 mcr p15,0,r0,c15,c2,4 213#endif 214 215 /* 216 * Go setup Memory and board specific bits prior to relocation. 217 */ 218 bl lowlevel_init /* go setup pll,mux,memory */ 219 220 bl _main 221 222/*------------------------------------------------------------------------------*/ 223 224 .globl c_runtime_cpu_setup 225c_runtime_cpu_setup: 226 227 mov pc, lr 228 229#ifndef CONFIG_SPL_BUILD 230/* 231 ************************************************************************* 232 * 233 * Interrupt handling 234 * 235 ************************************************************************* 236 */ 237@ 238@ IRQ stack frame. 239@ 240#define S_FRAME_SIZE 72 241 242#define S_OLD_R0 68 243#define S_PSR 64 244#define S_PC 60 245#define S_LR 56 246#define S_SP 52 247 248#define S_IP 48 249#define S_FP 44 250#define S_R10 40 251#define S_R9 36 252#define S_R8 32 253#define S_R7 28 254#define S_R6 24 255#define S_R5 20 256#define S_R4 16 257#define S_R3 12 258#define S_R2 8 259#define S_R1 4 260#define S_R0 0 261 262#define MODE_SVC 0x13 263#define I_BIT 0x80 264 265/* 266 * use bad_save_user_regs for abort/prefetch/undef/swi ... 267 */ 268 269 .macro bad_save_user_regs 270 /* carve out a frame on current user stack */ 271 sub sp, sp, #S_FRAME_SIZE 272 /* Save user registers (now in svc mode) r0-r12 */ 273 stmia sp, {r0 - r12} 274 275 ldr r2, IRQ_STACK_START_IN 276 /* get values for "aborted" pc and cpsr (into parm regs) */ 277 ldmia r2, {r2 - r3} 278 /* grab pointer to old stack */ 279 add r0, sp, #S_FRAME_SIZE 280 281 add r5, sp, #S_SP 282 mov r1, lr 283 /* save sp_SVC, lr_SVC, pc, cpsr */ 284 stmia r5, {r0 - r3} 285 /* save current stack into r0 (param register) */ 286 mov r0, sp 287 .endm 288 289 .macro get_bad_stack 290 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 291 292 /* save caller lr in position 0 of saved stack */ 293 str lr, [r13] 294 /* get the spsr */ 295 mrs lr, spsr 296 /* save spsr in position 1 of saved stack */ 297 str lr, [r13, #4] 298 299 /* prepare SVC-Mode */ 300 mov r13, #MODE_SVC 301 @ msr spsr_c, r13 302 /* switch modes, make sure moves will execute */ 303 msr spsr, r13 304 /* capture return pc */ 305 mov lr, pc 306 /* jump to next instruction & switch modes. */ 307 movs pc, lr 308 .endm 309 310 .macro get_bad_stack_swi 311 /* space on current stack for scratch reg. */ 312 sub r13, r13, #4 313 /* save R0's value. */ 314 str r0, [r13] 315 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 316 /* save caller lr in position 0 of saved stack */ 317 str lr, [r0] 318 /* get the spsr */ 319 mrs lr, spsr 320 /* save spsr in position 1 of saved stack */ 321 str lr, [r0, #4] 322 /* restore lr */ 323 ldr lr, [r0] 324 /* restore r0 */ 325 ldr r0, [r13] 326 /* pop stack entry */ 327 add r13, r13, #4 328 .endm 329 330/* 331 * exception handlers 332 */ 333 .align 5 334undefined_instruction: 335 get_bad_stack 336 bad_save_user_regs 337 bl do_undefined_instruction 338 339 .align 5 340software_interrupt: 341 get_bad_stack_swi 342 bad_save_user_regs 343 bl do_software_interrupt 344 345 .align 5 346prefetch_abort: 347 get_bad_stack 348 bad_save_user_regs 349 bl do_prefetch_abort 350 351 .align 5 352data_abort: 353 get_bad_stack 354 bad_save_user_regs 355 bl do_data_abort 356 357 .align 5 358not_used: 359 get_bad_stack 360 bad_save_user_regs 361 bl do_not_used 362 363 .align 5 364irq: 365 get_bad_stack 366 bad_save_user_regs 367 bl do_irq 368 369 .align 5 370fiq: 371 get_bad_stack 372 bad_save_user_regs 373 bl do_fiq 374#endif /* CONFIG_SPL_BUILD */ 375