1/* 2 * armboot - Startup Code for S3C6400/ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <config.h> 34#include <version.h> 35#ifdef CONFIG_ENABLE_MMU 36#include <asm/proc/domain.h> 37#endif 38#ifdef CONFIG_S3C64XX 39#include <asm/arch/s3c6400.h> 40#endif 41 42#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) 43#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 44#endif 45 46/* 47 ************************************************************************* 48 * 49 * Jump vector table as in table 3.1 in [1] 50 * 51 ************************************************************************* 52 */ 53 54.globl _start 55_start: b reset 56#ifndef CONFIG_NAND_SPL 57 ldr pc, _undefined_instruction 58 ldr pc, _software_interrupt 59 ldr pc, _prefetch_abort 60 ldr pc, _data_abort 61 ldr pc, _not_used 62 ldr pc, _irq 63 ldr pc, _fiq 64 65_undefined_instruction: 66 .word undefined_instruction 67_software_interrupt: 68 .word software_interrupt 69_prefetch_abort: 70 .word prefetch_abort 71_data_abort: 72 .word data_abort 73_not_used: 74 .word not_used 75_irq: 76 .word irq 77_fiq: 78 .word fiq 79_pad: 80 .word 0x12345678 /* now 16*4=64 */ 81#else 82 . = _start + 64 83#endif 84 85.global _end_vect 86_end_vect: 87 .balignl 16,0xdeadbeef 88/* 89 ************************************************************************* 90 * 91 * Startup Code (reset vector) 92 * 93 * do important init only if we don't start from memory! 94 * setup Memory and board specific bits prior to relocation. 95 * relocate armboot to ram 96 * setup stack 97 * 98 ************************************************************************* 99 */ 100 101_TEXT_BASE: 102 .word TEXT_BASE 103 104/* 105 * Below variable is very important because we use MMU in U-Boot. 106 * Without it, we cannot run code correctly before MMU is ON. 107 * by scsuh. 108 */ 109_TEXT_PHY_BASE: 110 .word CONFIG_SYS_PHY_UBOOT_BASE 111 112.globl _armboot_start 113_armboot_start: 114 .word _start 115 116/* 117 * These are defined in the board-specific linker script. 118 */ 119.globl _bss_start 120_bss_start: 121 .word __bss_start 122 123.globl _bss_end 124_bss_end: 125 .word _end 126 127/* 128 * the actual reset code 129 */ 130 131reset: 132 /* 133 * set the cpu to SVC32 mode 134 */ 135 mrs r0, cpsr 136 bic r0, r0, #0x3f 137 orr r0, r0, #0xd3 138 msr cpsr, r0 139 140/* 141 ************************************************************************* 142 * 143 * CPU_init_critical registers 144 * 145 * setup important registers 146 * setup memory timing 147 * 148 ************************************************************************* 149 */ 150 /* 151 * we do sys-critical inits only at reboot, 152 * not when booting from ram! 153 */ 154cpu_init_crit: 155 /* 156 * When booting from NAND - it has definitely been a reset, so, no need 157 * to flush caches and disable the MMU 158 */ 159#ifndef CONFIG_NAND_SPL 160 /* 161 * flush v4 I/D caches 162 */ 163 mov r0, #0 164 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 165 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 166 167 /* 168 * disable MMU stuff and caches 169 */ 170 mrc p15, 0, r0, c1, c0, 0 171 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 172 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 173 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 174 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 175 /* Prepare to disable the MMU */ 176 adr r1, mmu_disable_phys 177 /* We presume we're within the first 1024 bytes */ 178 and r1, r1, #0x3fc 179 ldr r2, _TEXT_PHY_BASE 180 ldr r3, =0xfff00000 181 and r2, r2, r3 182 orr r2, r2, r1 183 b mmu_disable 184 185 .align 5 186 /* Run in a single cache-line */ 187mmu_disable: 188 mcr p15, 0, r0, c1, c0, 0 189 nop 190 nop 191 mov pc, r2 192#endif 193 194mmu_disable_phys: 195#ifdef CONFIG_S3C64XX 196 /* Peri port setup */ 197 ldr r0, =0x70000000 198 orr r0, r0, #0x13 199 mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff) 200#endif 201 202 /* 203 * Go setup Memory and board specific bits prior to relocation. 204 */ 205 bl lowlevel_init /* go setup pll,mux,memory */ 206 207after_copy: 208#ifdef CONFIG_ENABLE_MMU 209enable_mmu: 210 /* enable domain access */ 211 ldr r5, =0x0000ffff 212 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ 213 214 /* Set the TTB register */ 215 ldr r0, _mmu_table_base 216 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE 217 ldr r2, =0xfff00000 218 bic r0, r0, r2 219 orr r1, r0, r1 220 mcr p15, 0, r1, c2, c0, 0 221 222 /* Enable the MMU */ 223 mrc p15, 0, r0, c1, c0, 0 224 orr r0, r0, #1 /* Set CR_M to enable MMU */ 225 226 /* Prepare to enable the MMU */ 227 adr r1, skip_hw_init 228 and r1, r1, #0x3fc 229 ldr r2, _TEXT_BASE 230 ldr r3, =0xfff00000 231 and r2, r2, r3 232 orr r2, r2, r1 233 b mmu_enable 234 235 .align 5 236 /* Run in a single cache-line */ 237mmu_enable: 238 239 mcr p15, 0, r0, c1, c0, 0 240 nop 241 nop 242 mov pc, r2 243#endif 244 245skip_hw_init: 246 /* Set up the stack */ 247stack_setup: 248 ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */ 249 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ 250 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ 251 sub sp, r0, #12 /* leave 3 words for abort-stack */ 252 253clear_bss: 254 ldr r0, _bss_start /* find start of bss segment */ 255 ldr r1, _bss_end /* stop here */ 256 mov r2, #0 /* clear */ 257 258clbss_l: 259 str r2, [r0] /* clear loop... */ 260 add r0, r0, #4 261 cmp r0, r1 262 ble clbss_l 263 264#ifndef CONFIG_NAND_SPL 265 ldr pc, _start_armboot 266 267_start_armboot: 268 .word start_armboot 269#else 270 b nand_boot 271/* .word nand_boot*/ 272#endif 273 274#ifdef CONFIG_ENABLE_MMU 275_mmu_table_base: 276 .word mmu_table 277#endif 278 279#ifndef CONFIG_NAND_SPL 280/* 281 * we assume that cache operation is done before. (eg. cleanup_before_linux()) 282 * actually, we don't need to do anything about cache if not use d-cache in 283 * U-Boot. So, in this function we clean only MMU. by scsuh 284 * 285 * void theLastJump(void *kernel, int arch_num, uint boot_params); 286 */ 287#ifdef CONFIG_ENABLE_MMU 288 .globl theLastJump 289theLastJump: 290 mov r9, r0 291 ldr r3, =0xfff00000 292 ldr r4, _TEXT_PHY_BASE 293 adr r5, phy_last_jump 294 bic r5, r5, r3 295 orr r5, r5, r4 296 mov pc, r5 297phy_last_jump: 298 /* 299 * disable MMU stuff 300 */ 301 mrc p15, 0, r0, c1, c0, 0 302 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 303 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 304 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 305 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 306 mcr p15, 0, r0, c1, c0, 0 307 308 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 309 310 mov r0, #0 311 mov pc, r9 312#endif 313/* 314 ************************************************************************* 315 * 316 * Interrupt handling 317 * 318 ************************************************************************* 319 */ 320@ 321@ IRQ stack frame. 322@ 323#define S_FRAME_SIZE 72 324 325#define S_OLD_R0 68 326#define S_PSR 64 327#define S_PC 60 328#define S_LR 56 329#define S_SP 52 330 331#define S_IP 48 332#define S_FP 44 333#define S_R10 40 334#define S_R9 36 335#define S_R8 32 336#define S_R7 28 337#define S_R6 24 338#define S_R5 20 339#define S_R4 16 340#define S_R3 12 341#define S_R2 8 342#define S_R1 4 343#define S_R0 0 344 345#define MODE_SVC 0x13 346#define I_BIT 0x80 347 348/* 349 * use bad_save_user_regs for abort/prefetch/undef/swi ... 350 */ 351 352 .macro bad_save_user_regs 353 /* carve out a frame on current user stack */ 354 sub sp, sp, #S_FRAME_SIZE 355 /* Save user registers (now in svc mode) r0-r12 */ 356 stmia sp, {r0 - r12} 357 358 ldr r2, _armboot_start 359 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) 360 /* set base 2 words into abort stack */ 361 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) 362 /* get values for "aborted" pc and cpsr (into parm regs) */ 363 ldmia r2, {r2 - r3} 364 /* grab pointer to old stack */ 365 add r0, sp, #S_FRAME_SIZE 366 367 add r5, sp, #S_SP 368 mov r1, lr 369 /* save sp_SVC, lr_SVC, pc, cpsr */ 370 stmia r5, {r0 - r3} 371 /* save current stack into r0 (param register) */ 372 mov r0, sp 373 .endm 374 375 .macro get_bad_stack 376 /* setup our mode stack (enter in banked mode) */ 377 ldr r13, _armboot_start 378 /* move past malloc pool */ 379 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) 380 /* move to reserved a couple spots for abort stack */ 381 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) 382 383 /* save caller lr in position 0 of saved stack */ 384 str lr, [r13] 385 /* get the spsr */ 386 mrs lr, spsr 387 /* save spsr in position 1 of saved stack */ 388 str lr, [r13, #4] 389 390 /* prepare SVC-Mode */ 391 mov r13, #MODE_SVC 392 @ msr spsr_c, r13 393 /* switch modes, make sure moves will execute */ 394 msr spsr, r13 395 /* capture return pc */ 396 mov lr, pc 397 /* jump to next instruction & switch modes. */ 398 movs pc, lr 399 .endm 400 401 .macro get_bad_stack_swi 402 /* space on current stack for scratch reg. */ 403 sub r13, r13, #4 404 /* save R0's value. */ 405 str r0, [r13] 406 /* get data regions start */ 407 ldr r0, _armboot_start 408 /* move past malloc pool */ 409 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) 410 /* move past gbl and a couple spots for abort stack */ 411 sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) 412 /* save caller lr in position 0 of saved stack */ 413 str lr, [r0] 414 /* get the spsr */ 415 mrs r0, spsr 416 /* save spsr in position 1 of saved stack */ 417 str lr, [r0, #4] 418 /* restore r0 */ 419 ldr r0, [r13] 420 /* pop stack entry */ 421 add r13, r13, #4 422 .endm 423 424/* 425 * exception handlers 426 */ 427 .align 5 428undefined_instruction: 429 get_bad_stack 430 bad_save_user_regs 431 bl do_undefined_instruction 432 433 .align 5 434software_interrupt: 435 get_bad_stack_swi 436 bad_save_user_regs 437 bl do_software_interrupt 438 439 .align 5 440prefetch_abort: 441 get_bad_stack 442 bad_save_user_regs 443 bl do_prefetch_abort 444 445 .align 5 446data_abort: 447 get_bad_stack 448 bad_save_user_regs 449 bl do_data_abort 450 451 .align 5 452not_used: 453 get_bad_stack 454 bad_save_user_regs 455 bl do_not_used 456 457 .align 5 458irq: 459 get_bad_stack 460 bad_save_user_regs 461 bl do_irq 462 463 .align 5 464fiq: 465 get_bad_stack 466 bad_save_user_regs 467 bl do_fiq 468#endif /* CONFIG_NAND_SPL */ 469