1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 * 11 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 12 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 13 * jsgood (jsgood.yang@samsung.com) 14 * Base codes by scsuh (sc.suh) 15 */ 16 17#include <asm-offsets.h> 18#include <config.h> 19#include <version.h> 20 21#ifndef CONFIG_SYS_PHY_UBOOT_BASE 22#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 23#endif 24 25/* 26 ************************************************************************* 27 * 28 * Startup Code (reset vector) 29 * 30 * do important init only if we don't start from memory! 31 * setup Memory and board specific bits prior to relocation. 32 * relocate armboot to ram 33 * setup stack 34 * 35 ************************************************************************* 36 */ 37 38 .globl reset 39 40reset: 41 /* 42 * set the cpu to SVC32 mode 43 */ 44 mrs r0, cpsr 45 bic r0, r0, #0x3f 46 orr r0, r0, #0xd3 47 msr cpsr, r0 48 49/* 50 ************************************************************************* 51 * 52 * CPU_init_critical registers 53 * 54 * setup important registers 55 * setup memory timing 56 * 57 ************************************************************************* 58 */ 59 /* 60 * we do sys-critical inits only at reboot, 61 * not when booting from ram! 62 */ 63cpu_init_crit: 64 /* 65 * When booting from NAND - it has definitely been a reset, so, no need 66 * to flush caches and disable the MMU 67 */ 68#ifndef CONFIG_SPL_BUILD 69 /* 70 * flush v4 I/D caches 71 */ 72 mov r0, #0 73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 75 76 /* 77 * disable MMU stuff and caches 78 */ 79 mrc p15, 0, r0, c1, c0, 0 80 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 81 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 82 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 83 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 84 85 /* Prepare to disable the MMU */ 86 adr r2, mmu_disable_phys 87 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 88 b mmu_disable 89 90 .align 5 91 /* Run in a single cache-line */ 92mmu_disable: 93 mcr p15, 0, r0, c1, c0, 0 94 nop 95 nop 96 mov pc, r2 97mmu_disable_phys: 98 99#ifdef CONFIG_DISABLE_TCM 100 /* 101 * Disable the TCMs 102 */ 103 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 104 cmp r0, #0 105 beq skip_tcmdisable 106 mov r1, #0 107 mov r2, #1 108 tst r0, r2 109 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 110 tst r0, r2, LSL #16 111 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 112skip_tcmdisable: 113#endif 114#endif 115 116#ifdef CONFIG_PERIPORT_REMAP 117 /* Peri port setup */ 118 ldr r0, =CONFIG_PERIPORT_BASE 119 orr r0, r0, #CONFIG_PERIPORT_SIZE 120 mcr p15,0,r0,c15,c2,4 121#endif 122 123 /* 124 * Go setup Memory and board specific bits prior to relocation. 125 */ 126 bl lowlevel_init /* go setup pll,mux,memory */ 127 128 bl _main 129 130/*------------------------------------------------------------------------------*/ 131 132 .globl c_runtime_cpu_setup 133c_runtime_cpu_setup: 134 135 mov pc, lr 136