xref: /openbmc/u-boot/arch/arm/cpu/arm1136/start.S (revision fa6c7413) 
1/*
2 *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
3 *
4 *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
5 *
6 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
7 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
8 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
9 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
10 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <asm-offsets.h>
32#include <config.h>
33#include <version.h>
34.globl _start
35_start: b	reset
36#ifdef CONFIG_SPL_BUILD
37	ldr	pc, _hang
38	ldr	pc, _hang
39	ldr	pc, _hang
40	ldr	pc, _hang
41	ldr	pc, _hang
42	ldr	pc, _hang
43	ldr	pc, _hang
44
45_hang:
46	.word	do_hang
47	.word	0x12345678
48	.word	0x12345678
49	.word	0x12345678
50	.word	0x12345678
51	.word	0x12345678
52	.word	0x12345678
53	.word	0x12345678	/* now 16*4=64 */
54#else
55	ldr	pc, _undefined_instruction
56	ldr	pc, _software_interrupt
57	ldr	pc, _prefetch_abort
58	ldr	pc, _data_abort
59	ldr	pc, _not_used
60	ldr	pc, _irq
61	ldr	pc, _fiq
62
63_undefined_instruction: .word undefined_instruction
64_software_interrupt:	.word software_interrupt
65_prefetch_abort:	.word prefetch_abort
66_data_abort:		.word data_abort
67_not_used:		.word not_used
68_irq:			.word irq
69_fiq:			.word fiq
70_pad:			.word 0x12345678 /* now 16*4=64 */
71#endif	/* CONFIG_SPL_BUILD */
72.global _end_vect
73_end_vect:
74
75	.balignl 16,0xdeadbeef
76/*
77 *************************************************************************
78 *
79 * Startup Code (reset vector)
80 *
81 * do important init only if we don't start from memory!
82 * setup Memory and board specific bits prior to relocation.
83 * relocate armboot to ram
84 * setup stack
85 *
86 *************************************************************************
87 */
88
89.globl _TEXT_BASE
90_TEXT_BASE:
91#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
92	.word	CONFIG_SPL_TEXT_BASE
93#else
94	.word	CONFIG_SYS_TEXT_BASE
95#endif
96
97/*
98 * These are defined in the board-specific linker script.
99 * Subtracting _start from them lets the linker put their
100 * relative position in the executable instead of leaving
101 * them null.
102 */
103.globl _bss_start_ofs
104_bss_start_ofs:
105	.word __bss_start - _start
106
107.globl _bss_end_ofs
108_bss_end_ofs:
109	.word __bss_end - _start
110
111.globl _end_ofs
112_end_ofs:
113	.word _end - _start
114
115#ifdef CONFIG_USE_IRQ
116/* IRQ stack memory (calculated at run-time) */
117.globl IRQ_STACK_START
118IRQ_STACK_START:
119	.word	0x0badc0de
120
121/* IRQ stack memory (calculated at run-time) */
122.globl FIQ_STACK_START
123FIQ_STACK_START:
124	.word 0x0badc0de
125#endif
126
127/* IRQ stack memory (calculated at run-time) + 8 bytes */
128.globl IRQ_STACK_START_IN
129IRQ_STACK_START_IN:
130	.word	0x0badc0de
131
132/*
133 * the actual reset code
134 */
135
136reset:
137	/*
138	 * set the cpu to SVC32 mode
139	 */
140	mrs	r0,cpsr
141	bic	r0,r0,#0x1f
142	orr	r0,r0,#0xd3
143	msr	cpsr,r0
144
145#ifdef CONFIG_OMAP2420H4
146       /* Copy vectors to mask ROM indirect addr */
147	adr	r0, _start		/* r0 <- current position of code   */
148		add     r0, r0, #4				/* skip reset vector			*/
149	mov	r2, #64			/* r2 <- size to copy  */
150	add	r2, r0, r2		/* r2 <- source end address	    */
151	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
152	mov	r3, #SRAM_OFFSET1
153	add	r1, r1, r3
154	mov	r3, #SRAM_OFFSET2
155	add	r1, r1, r3
156next:
157	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
158	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
159	cmp	r0, r2			/* until source end address [r2]    */
160	bne	next			/* loop until equal */
161	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
162#endif
163	/* the mask ROM code should have PLL and others stable */
164#ifndef CONFIG_SKIP_LOWLEVEL_INIT
165	bl  cpu_init_crit
166#endif
167
168	bl	_main
169
170/*------------------------------------------------------------------------------*/
171
172#ifndef CONFIG_SPL_BUILD
173/*
174 * void relocate_code(addr_moni)
175 *
176 * This function relocates the monitor code.
177 */
178	.globl	relocate_code
179relocate_code:
180	mov	r6, r0	/* save addr of destination */
181
182	adr	r0, _start
183	subs	r9, r6, r0		/* r9 <- relocation offset */
184	beq	relocate_done		/* skip relocation */
185	mov	r1, r6			/* r1 <- scratch for copy_loop */
186	ldr	r3, _image_copy_end_ofs
187	add	r2, r0, r3		/* r2 <- source end address	    */
188
189copy_loop:
190	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
191	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
192	cmp	r0, r2			/* until source end address [r2]    */
193	blo	copy_loop
194
195	/*
196	 * fix .rel.dyn relocations
197	 */
198	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
199	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
200	add	r10, r10, r0		/* r10 <- sym table in FLASH */
201	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
202	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
203	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
204	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
205fixloop:
206	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
207	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
208	ldr	r1, [r2, #4]
209	and	r7, r1, #0xff
210	cmp	r7, #23			/* relative fixup? */
211	beq	fixrel
212	cmp	r7, #2			/* absolute fixup? */
213	beq	fixabs
214	/* ignore unknown type of fixup */
215	b	fixnext
216fixabs:
217	/* absolute fix: set location to (offset) symbol value */
218	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
219	add	r1, r10, r1		/* r1 <- address of symbol in table */
220	ldr	r1, [r1, #4]		/* r1 <- symbol value */
221	add	r1, r1, r9		/* r1 <- relocated sym addr */
222	b	fixnext
223fixrel:
224	/* relative fix: increase location by offset */
225	ldr	r1, [r0]
226	add	r1, r1, r9
227fixnext:
228	str	r1, [r0]
229	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
230	cmp	r2, r3
231	blo	fixloop
232
233relocate_done:
234
235	bx	lr
236
237_image_copy_end_ofs:
238	.word __image_copy_end - _start
239_rel_dyn_start_ofs:
240	.word __rel_dyn_start - _start
241_rel_dyn_end_ofs:
242	.word __rel_dyn_end - _start
243_dynsym_start_ofs:
244	.word __dynsym_start - _start
245
246#endif
247
248	.globl	c_runtime_cpu_setup
249c_runtime_cpu_setup:
250
251	bx	lr
252
253/*
254 *************************************************************************
255 *
256 * CPU_init_critical registers
257 *
258 * setup important registers
259 * setup memory timing
260 *
261 *************************************************************************
262 */
263#ifndef CONFIG_SKIP_LOWLEVEL_INIT
264cpu_init_crit:
265	/*
266	 * flush v4 I/D caches
267	 */
268	mov	r0, #0
269	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
270	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
271
272	/*
273	 * disable MMU stuff and caches
274	 */
275	mrc	p15, 0, r0, c1, c0, 0
276	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
277	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
278	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
279	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
280	mcr	p15, 0, r0, c1, c0, 0
281
282	/*
283	 * Jump to board specific initialization... The Mask ROM will have already initialized
284	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
285	 */
286	mov	ip, lr		/* persevere link reg across call */
287	bl	lowlevel_init	/* go setup pll,mux,memory */
288	mov	lr, ip		/* restore link */
289	mov	pc, lr		/* back to my caller */
290#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
291
292#ifndef CONFIG_SPL_BUILD
293/*
294 *************************************************************************
295 *
296 * Interrupt handling
297 *
298 *************************************************************************
299 */
300@
301@ IRQ stack frame.
302@
303#define S_FRAME_SIZE	72
304
305#define S_OLD_R0	68
306#define S_PSR		64
307#define S_PC		60
308#define S_LR		56
309#define S_SP		52
310
311#define S_IP		48
312#define S_FP		44
313#define S_R10		40
314#define S_R9		36
315#define S_R8		32
316#define S_R7		28
317#define S_R6		24
318#define S_R5		20
319#define S_R4		16
320#define S_R3		12
321#define S_R2		8
322#define S_R1		4
323#define S_R0		0
324
325#define MODE_SVC 0x13
326#define I_BIT	 0x80
327
328/*
329 * use bad_save_user_regs for abort/prefetch/undef/swi ...
330 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
331 */
332
333	.macro	bad_save_user_regs
334	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
335	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
336
337	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
338	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
339	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
340
341	add	r5, sp, #S_SP
342	mov	r1, lr
343	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
344	mov	r0, sp				@ save current stack into r0 (param register)
345	.endm
346
347	.macro	irq_save_user_regs
348	sub	sp, sp, #S_FRAME_SIZE
349	stmia	sp, {r0 - r12}			@ Calling r0-r12
350	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
351	stmdb	r8, {sp, lr}^			@ Calling SP, LR
352	str	lr, [r8, #0]			@ Save calling PC
353	mrs	r6, spsr
354	str	r6, [r8, #4]			@ Save CPSR
355	str	r0, [r8, #8]			@ Save OLD_R0
356	mov	r0, sp
357	.endm
358
359	.macro	irq_restore_user_regs
360	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
361	mov	r0, r0
362	ldr	lr, [sp, #S_PC]			@ Get PC
363	add	sp, sp, #S_FRAME_SIZE
364	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
365	.endm
366
367	.macro get_bad_stack
368	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
369
370	str	lr, [r13]			@ save caller lr in position 0 of saved stack
371	mrs	lr, spsr			@ get the spsr
372	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
373
374	mov	r13, #MODE_SVC			@ prepare SVC-Mode
375	@ msr	spsr_c, r13
376	msr	spsr, r13			@ switch modes, make sure moves will execute
377	mov	lr, pc				@ capture return pc
378	movs	pc, lr				@ jump to next instruction & switch modes.
379	.endm
380
381	.macro get_bad_stack_swi
382	sub	r13, r13, #4			@ space on current stack for scratch reg.
383	str	r0, [r13]			@ save R0's value.
384	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
385	str	lr, [r0]			@ save caller lr in position 0 of saved stack
386	mrs	lr, spsr			@ get the spsr
387	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
388	ldr	lr, [r0]			@ restore lr
389	ldr	r0, [r13]			@ restore r0
390	add	r13, r13, #4			@ pop stack entry
391	.endm
392
393	.macro get_irq_stack			@ setup IRQ stack
394	ldr	sp, IRQ_STACK_START
395	.endm
396
397	.macro get_fiq_stack			@ setup FIQ stack
398	ldr	sp, FIQ_STACK_START
399	.endm
400#endif	/* CONFIG_SPL_BUILD */
401
402/*
403 * exception handlers
404 */
405#ifdef CONFIG_SPL_BUILD
406	.align	5
407do_hang:
408	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
409	bl	hang				/* hang and never return */
410#else	/* !CONFIG_SPL_BUILD */
411	.align	5
412undefined_instruction:
413	get_bad_stack
414	bad_save_user_regs
415	bl	do_undefined_instruction
416
417	.align	5
418software_interrupt:
419	get_bad_stack_swi
420	bad_save_user_regs
421	bl	do_software_interrupt
422
423	.align	5
424prefetch_abort:
425	get_bad_stack
426	bad_save_user_regs
427	bl	do_prefetch_abort
428
429	.align	5
430data_abort:
431	get_bad_stack
432	bad_save_user_regs
433	bl	do_data_abort
434
435	.align	5
436not_used:
437	get_bad_stack
438	bad_save_user_regs
439	bl	do_not_used
440
441#ifdef CONFIG_USE_IRQ
442
443	.align	5
444irq:
445	get_irq_stack
446	irq_save_user_regs
447	bl	do_irq
448	irq_restore_user_regs
449
450	.align	5
451fiq:
452	get_fiq_stack
453	/* someone ought to write a more effiction fiq_save_user_regs */
454	irq_save_user_regs
455	bl	do_fiq
456	irq_restore_user_regs
457
458#else
459
460	.align	5
461irq:
462	get_bad_stack
463	bad_save_user_regs
464	bl	do_irq
465
466	.align	5
467fiq:
468	get_bad_stack
469	bad_save_user_regs
470	bl	do_fiq
471
472#endif
473	.align 5
474.global arm1136_cache_flush
475arm1136_cache_flush:
476#if !defined(CONFIG_SYS_ICACHE_OFF)
477		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
478#endif
479#if !defined(CONFIG_SYS_DCACHE_OFF)
480		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
481#endif
482		mov	pc, lr			@ back to caller
483#endif	/* CONFIG_SPL_BUILD */
484