1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15#include <asm-offsets.h> 16#include <config.h> 17#include <version.h> 18 19/* 20 ************************************************************************* 21 * 22 * Startup Code (reset vector) 23 * 24 * do important init only if we don't start from memory! 25 * setup Memory and board specific bits prior to relocation. 26 * relocate armboot to ram 27 * setup stack 28 * 29 ************************************************************************* 30 */ 31 32 .globl reset 33 34reset: 35 /* 36 * set the cpu to SVC32 mode 37 */ 38 mrs r0,cpsr 39 bic r0,r0,#0x1f 40 orr r0,r0,#0xd3 41 msr cpsr,r0 42 43 /* the mask ROM code should have PLL and others stable */ 44#ifndef CONFIG_SKIP_LOWLEVEL_INIT 45 bl cpu_init_crit 46#endif 47 48 bl _main 49 50/*------------------------------------------------------------------------------*/ 51 52 .globl c_runtime_cpu_setup 53c_runtime_cpu_setup: 54 55 bx lr 56 57/* 58 ************************************************************************* 59 * 60 * CPU_init_critical registers 61 * 62 * setup important registers 63 * setup memory timing 64 * 65 ************************************************************************* 66 */ 67#ifndef CONFIG_SKIP_LOWLEVEL_INIT 68cpu_init_crit: 69 /* 70 * flush v4 I/D caches 71 */ 72 mov r0, #0 73 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 74 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 75 76 /* 77 * disable MMU stuff and caches 78 */ 79 mrc p15, 0, r0, c1, c0, 0 80 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 81 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 82 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 83 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 84 mcr p15, 0, r0, c1, c0, 0 85 86 /* 87 * Jump to board specific initialization... The Mask ROM will have already initialized 88 * basic memory. Go here to bump up clock rate and handle wake up conditions. 89 */ 90 mov ip, lr /* persevere link reg across call */ 91 bl lowlevel_init /* go setup pll,mux,memory */ 92 mov lr, ip /* restore link */ 93 mov pc, lr /* back to my caller */ 94#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 95