1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word __bss_end__ - _start 106 107.globl _end_ofs 108_end_ofs: 109 .word _end - _start 110 111#ifdef CONFIG_USE_IRQ 112/* IRQ stack memory (calculated at run-time) */ 113.globl IRQ_STACK_START 114IRQ_STACK_START: 115 .word 0x0badc0de 116 117/* IRQ stack memory (calculated at run-time) */ 118.globl FIQ_STACK_START 119FIQ_STACK_START: 120 .word 0x0badc0de 121#endif 122 123/* IRQ stack memory (calculated at run-time) + 8 bytes */ 124.globl IRQ_STACK_START_IN 125IRQ_STACK_START_IN: 126 .word 0x0badc0de 127 128/* 129 * the actual reset code 130 */ 131 132reset: 133 /* 134 * set the cpu to SVC32 mode 135 */ 136 mrs r0,cpsr 137 bic r0,r0,#0x1f 138 orr r0,r0,#0xd3 139 msr cpsr,r0 140 141#ifdef CONFIG_OMAP2420H4 142 /* Copy vectors to mask ROM indirect addr */ 143 adr r0, _start /* r0 <- current position of code */ 144 add r0, r0, #4 /* skip reset vector */ 145 mov r2, #64 /* r2 <- size to copy */ 146 add r2, r0, r2 /* r2 <- source end address */ 147 mov r1, #SRAM_OFFSET0 /* build vect addr */ 148 mov r3, #SRAM_OFFSET1 149 add r1, r1, r3 150 mov r3, #SRAM_OFFSET2 151 add r1, r1, r3 152next: 153 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 154 stmia r1!, {r3-r10} /* copy to target address [r1] */ 155 cmp r0, r2 /* until source end address [r2] */ 156 bne next /* loop until equal */ 157 bl cpy_clk_code /* put dpll adjust code behind vectors */ 158#endif 159 /* the mask ROM code should have PLL and others stable */ 160#ifndef CONFIG_SKIP_LOWLEVEL_INIT 161 bl cpu_init_crit 162#endif 163 164/* Set stackpointer in internal RAM to call board_init_f */ 165call_board_init_f: 166 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 167 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 168 ldr r0,=0x00000000 169 170 bl board_init_f 171 172/*------------------------------------------------------------------------------*/ 173 174/* 175 * void relocate_code (addr_sp, gd, addr_moni) 176 * 177 * This "function" does not return, instead it continues in RAM 178 * after relocating the monitor code. 179 * 180 */ 181 .globl relocate_code 182relocate_code: 183 mov r4, r0 /* save addr_sp */ 184 mov r5, r1 /* save addr of gd */ 185 mov r6, r2 /* save addr of destination */ 186 187 /* Set up the stack */ 188stack_setup: 189 mov sp, r4 190 191 adr r0, _start 192 cmp r0, r6 193 beq clear_bss /* skip relocation */ 194 mov r1, r6 /* r1 <- scratch for copy_loop */ 195 ldr r3, _bss_start_ofs 196 add r2, r0, r3 /* r2 <- source end address */ 197 198copy_loop: 199 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 200 stmia r1!, {r9-r10} /* copy to target address [r1] */ 201 cmp r0, r2 /* until source end address [r2] */ 202 blo copy_loop 203 204#ifndef CONFIG_SPL_BUILD 205 /* 206 * fix .rel.dyn relocations 207 */ 208 ldr r0, _TEXT_BASE /* r0 <- Text base */ 209 sub r9, r6, r0 /* r9 <- relocation offset */ 210 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 211 add r10, r10, r0 /* r10 <- sym table in FLASH */ 212 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 213 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 214 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 215 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 216fixloop: 217 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 218 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 219 ldr r1, [r2, #4] 220 and r7, r1, #0xff 221 cmp r7, #23 /* relative fixup? */ 222 beq fixrel 223 cmp r7, #2 /* absolute fixup? */ 224 beq fixabs 225 /* ignore unknown type of fixup */ 226 b fixnext 227fixabs: 228 /* absolute fix: set location to (offset) symbol value */ 229 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 230 add r1, r10, r1 /* r1 <- address of symbol in table */ 231 ldr r1, [r1, #4] /* r1 <- symbol value */ 232 add r1, r1, r9 /* r1 <- relocated sym addr */ 233 b fixnext 234fixrel: 235 /* relative fix: increase location by offset */ 236 ldr r1, [r0] 237 add r1, r1, r9 238fixnext: 239 str r1, [r0] 240 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 241 cmp r2, r3 242 blo fixloop 243#endif 244 245clear_bss: 246#ifndef CONFIG_SPL_BUILD 247 ldr r0, _bss_start_ofs 248 ldr r1, _bss_end_ofs 249 mov r4, r6 /* reloc addr */ 250 add r0, r0, r4 251 add r1, r1, r4 252 mov r2, #0x00000000 /* clear */ 253 254clbss_l:cmp r0, r1 /* clear loop... */ 255 bhs clbss_e /* if reached end of bss, exit */ 256 str r2, [r0] 257 add r0, r0, #4 258 b clbss_l 259clbss_e: 260#endif /* #ifndef CONFIG_SPL_BUILD */ 261 262/* 263 * We are done. Do not return, instead branch to second part of board 264 * initialization, now running from RAM. 265 */ 266#ifdef CONFIG_NAND_SPL 267 ldr r0, _nand_boot_ofs 268 mov pc, r0 269 270_nand_boot_ofs: 271 .word nand_boot 272#else 273jump_2_ram: 274 ldr r0, _board_init_r_ofs 275 ldr r1, _TEXT_BASE 276 add lr, r0, r1 277 add lr, lr, r9 278 /* setup parameters for board_init_r */ 279 mov r0, r5 /* gd_t */ 280 mov r1, r6 /* dest_addr */ 281 /* jump to it ... */ 282 mov pc, lr 283 284_board_init_r_ofs: 285 .word board_init_r - _start 286#endif 287 288_rel_dyn_start_ofs: 289 .word __rel_dyn_start - _start 290_rel_dyn_end_ofs: 291 .word __rel_dyn_end - _start 292_dynsym_start_ofs: 293 .word __dynsym_start - _start 294 295/* 296 ************************************************************************* 297 * 298 * CPU_init_critical registers 299 * 300 * setup important registers 301 * setup memory timing 302 * 303 ************************************************************************* 304 */ 305#ifndef CONFIG_SKIP_LOWLEVEL_INIT 306cpu_init_crit: 307 /* 308 * flush v4 I/D caches 309 */ 310 mov r0, #0 311 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 312 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 313 314 /* 315 * disable MMU stuff and caches 316 */ 317 mrc p15, 0, r0, c1, c0, 0 318 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 319 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 320 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 321 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 322 mcr p15, 0, r0, c1, c0, 0 323 324 /* 325 * Jump to board specific initialization... The Mask ROM will have already initialized 326 * basic memory. Go here to bump up clock rate and handle wake up conditions. 327 */ 328 mov ip, lr /* persevere link reg across call */ 329 bl lowlevel_init /* go setup pll,mux,memory */ 330 mov lr, ip /* restore link */ 331 mov pc, lr /* back to my caller */ 332#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 333 334#ifndef CONFIG_SPL_BUILD 335/* 336 ************************************************************************* 337 * 338 * Interrupt handling 339 * 340 ************************************************************************* 341 */ 342@ 343@ IRQ stack frame. 344@ 345#define S_FRAME_SIZE 72 346 347#define S_OLD_R0 68 348#define S_PSR 64 349#define S_PC 60 350#define S_LR 56 351#define S_SP 52 352 353#define S_IP 48 354#define S_FP 44 355#define S_R10 40 356#define S_R9 36 357#define S_R8 32 358#define S_R7 28 359#define S_R6 24 360#define S_R5 20 361#define S_R4 16 362#define S_R3 12 363#define S_R2 8 364#define S_R1 4 365#define S_R0 0 366 367#define MODE_SVC 0x13 368#define I_BIT 0x80 369 370/* 371 * use bad_save_user_regs for abort/prefetch/undef/swi ... 372 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 373 */ 374 375 .macro bad_save_user_regs 376 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 377 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 378 379 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 380 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 381 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 382 383 add r5, sp, #S_SP 384 mov r1, lr 385 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 386 mov r0, sp @ save current stack into r0 (param register) 387 .endm 388 389 .macro irq_save_user_regs 390 sub sp, sp, #S_FRAME_SIZE 391 stmia sp, {r0 - r12} @ Calling r0-r12 392 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 393 stmdb r8, {sp, lr}^ @ Calling SP, LR 394 str lr, [r8, #0] @ Save calling PC 395 mrs r6, spsr 396 str r6, [r8, #4] @ Save CPSR 397 str r0, [r8, #8] @ Save OLD_R0 398 mov r0, sp 399 .endm 400 401 .macro irq_restore_user_regs 402 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 403 mov r0, r0 404 ldr lr, [sp, #S_PC] @ Get PC 405 add sp, sp, #S_FRAME_SIZE 406 subs pc, lr, #4 @ return & move spsr_svc into cpsr 407 .endm 408 409 .macro get_bad_stack 410 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 411 412 str lr, [r13] @ save caller lr in position 0 of saved stack 413 mrs lr, spsr @ get the spsr 414 str lr, [r13, #4] @ save spsr in position 1 of saved stack 415 416 mov r13, #MODE_SVC @ prepare SVC-Mode 417 @ msr spsr_c, r13 418 msr spsr, r13 @ switch modes, make sure moves will execute 419 mov lr, pc @ capture return pc 420 movs pc, lr @ jump to next instruction & switch modes. 421 .endm 422 423 .macro get_bad_stack_swi 424 sub r13, r13, #4 @ space on current stack for scratch reg. 425 str r0, [r13] @ save R0's value. 426 ldr r0, IRQ_STACK_START_IN @ get data regions start 427 str lr, [r0] @ save caller lr in position 0 of saved stack 428 mrs r0, spsr @ get the spsr 429 str lr, [r0, #4] @ save spsr in position 1 of saved stack 430 ldr r0, [r13] @ restore r0 431 add r13, r13, #4 @ pop stack entry 432 .endm 433 434 .macro get_irq_stack @ setup IRQ stack 435 ldr sp, IRQ_STACK_START 436 .endm 437 438 .macro get_fiq_stack @ setup FIQ stack 439 ldr sp, FIQ_STACK_START 440 .endm 441#endif /* CONFIG_SPL_BUILD */ 442 443/* 444 * exception handlers 445 */ 446#ifdef CONFIG_SPL_BUILD 447 .align 5 448do_hang: 449 ldr sp, _TEXT_BASE /* use 32 words about stack */ 450 bl hang /* hang and never return */ 451#else /* !CONFIG_SPL_BUILD */ 452 .align 5 453undefined_instruction: 454 get_bad_stack 455 bad_save_user_regs 456 bl do_undefined_instruction 457 458 .align 5 459software_interrupt: 460 get_bad_stack_swi 461 bad_save_user_regs 462 bl do_software_interrupt 463 464 .align 5 465prefetch_abort: 466 get_bad_stack 467 bad_save_user_regs 468 bl do_prefetch_abort 469 470 .align 5 471data_abort: 472 get_bad_stack 473 bad_save_user_regs 474 bl do_data_abort 475 476 .align 5 477not_used: 478 get_bad_stack 479 bad_save_user_regs 480 bl do_not_used 481 482#ifdef CONFIG_USE_IRQ 483 484 .align 5 485irq: 486 get_irq_stack 487 irq_save_user_regs 488 bl do_irq 489 irq_restore_user_regs 490 491 .align 5 492fiq: 493 get_fiq_stack 494 /* someone ought to write a more effiction fiq_save_user_regs */ 495 irq_save_user_regs 496 bl do_fiq 497 irq_restore_user_regs 498 499#else 500 501 .align 5 502irq: 503 get_bad_stack 504 bad_save_user_regs 505 bl do_irq 506 507 .align 5 508fiq: 509 get_bad_stack 510 bad_save_user_regs 511 bl do_fiq 512 513#endif 514 .align 5 515.global arm1136_cache_flush 516arm1136_cache_flush: 517#if !defined(CONFIG_SYS_ICACHE_OFF) 518 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 519#endif 520#if !defined(CONFIG_SYS_DCACHE_OFF) 521 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 522#endif 523 mov pc, lr @ back to caller 524#endif /* CONFIG_SPL_BUILD */ 525