xref: /openbmc/u-boot/arch/arm/cpu/arm1136/start.S (revision bf48fcb6) 
1/*
2 *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
3 *
4 *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
5 *
6 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
7 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
8 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
9 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
10 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <asm-offsets.h>
32#include <config.h>
33#include <version.h>
34.globl _start
35_start: b	reset
36#ifdef CONFIG_SPL_BUILD
37	ldr	pc, _hang
38	ldr	pc, _hang
39	ldr	pc, _hang
40	ldr	pc, _hang
41	ldr	pc, _hang
42	ldr	pc, _hang
43	ldr	pc, _hang
44
45_hang:
46	.word	do_hang
47	.word	0x12345678
48	.word	0x12345678
49	.word	0x12345678
50	.word	0x12345678
51	.word	0x12345678
52	.word	0x12345678
53	.word	0x12345678	/* now 16*4=64 */
54#else
55	ldr	pc, _undefined_instruction
56	ldr	pc, _software_interrupt
57	ldr	pc, _prefetch_abort
58	ldr	pc, _data_abort
59	ldr	pc, _not_used
60	ldr	pc, _irq
61	ldr	pc, _fiq
62
63_undefined_instruction: .word undefined_instruction
64_software_interrupt:	.word software_interrupt
65_prefetch_abort:	.word prefetch_abort
66_data_abort:		.word data_abort
67_not_used:		.word not_used
68_irq:			.word irq
69_fiq:			.word fiq
70_pad:			.word 0x12345678 /* now 16*4=64 */
71#endif	/* CONFIG_SPL_BUILD */
72.global _end_vect
73_end_vect:
74
75	.balignl 16,0xdeadbeef
76/*
77 *************************************************************************
78 *
79 * Startup Code (reset vector)
80 *
81 * do important init only if we don't start from memory!
82 * setup Memory and board specific bits prior to relocation.
83 * relocate armboot to ram
84 * setup stack
85 *
86 *************************************************************************
87 */
88
89.globl _TEXT_BASE
90_TEXT_BASE:
91	.word	CONFIG_SYS_TEXT_BASE
92
93/*
94 * These are defined in the board-specific linker script.
95 * Subtracting _start from them lets the linker put their
96 * relative position in the executable instead of leaving
97 * them null.
98 */
99.globl _bss_start_ofs
100_bss_start_ofs:
101	.word __bss_start - _start
102
103.global	_image_copy_end_ofs
104_image_copy_end_ofs:
105	.word 	__image_copy_end - _start
106
107.globl _bss_end_ofs
108_bss_end_ofs:
109	.word __bss_end__ - _start
110
111.globl _end_ofs
112_end_ofs:
113	.word _end - _start
114
115#ifdef CONFIG_USE_IRQ
116/* IRQ stack memory (calculated at run-time) */
117.globl IRQ_STACK_START
118IRQ_STACK_START:
119	.word	0x0badc0de
120
121/* IRQ stack memory (calculated at run-time) */
122.globl FIQ_STACK_START
123FIQ_STACK_START:
124	.word 0x0badc0de
125#endif
126
127/* IRQ stack memory (calculated at run-time) + 8 bytes */
128.globl IRQ_STACK_START_IN
129IRQ_STACK_START_IN:
130	.word	0x0badc0de
131
132/*
133 * the actual reset code
134 */
135
136reset:
137	/*
138	 * set the cpu to SVC32 mode
139	 */
140	mrs	r0,cpsr
141	bic	r0,r0,#0x1f
142	orr	r0,r0,#0xd3
143	msr	cpsr,r0
144
145#ifdef CONFIG_OMAP2420H4
146       /* Copy vectors to mask ROM indirect addr */
147	adr	r0, _start		/* r0 <- current position of code   */
148		add     r0, r0, #4				/* skip reset vector			*/
149	mov	r2, #64			/* r2 <- size to copy  */
150	add	r2, r0, r2		/* r2 <- source end address	    */
151	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
152	mov	r3, #SRAM_OFFSET1
153	add	r1, r1, r3
154	mov	r3, #SRAM_OFFSET2
155	add	r1, r1, r3
156next:
157	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
158	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
159	cmp	r0, r2			/* until source end address [r2]    */
160	bne	next			/* loop until equal */
161	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
162#endif
163	/* the mask ROM code should have PLL and others stable */
164#ifndef CONFIG_SKIP_LOWLEVEL_INIT
165	bl  cpu_init_crit
166#endif
167
168	bl	_main
169
170/*------------------------------------------------------------------------------*/
171
172/*
173 * void relocate_code (addr_sp, gd, addr_moni)
174 *
175 * This "function" does not return, instead it continues in RAM
176 * after relocating the monitor code.
177 *
178 */
179	.globl	relocate_code
180relocate_code:
181	mov	r4, r0	/* save addr_sp */
182	mov	r5, r1	/* save addr of gd */
183	mov	r6, r2	/* save addr of destination */
184
185	adr	r0, _start
186	cmp	r0, r6
187	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
188	beq	relocate_done		/* skip relocation */
189	mov	r1, r6			/* r1 <- scratch for copy_loop */
190	ldr	r3, _image_copy_end_ofs
191	add	r2, r0, r3		/* r2 <- source end address	    */
192
193copy_loop:
194	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
195	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
196	cmp	r0, r2			/* until source end address [r2]    */
197	blo	copy_loop
198
199#ifndef CONFIG_SPL_BUILD
200	/*
201	 * fix .rel.dyn relocations
202	 */
203	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
204	sub	r9, r6, r0		/* r9 <- relocation offset */
205	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
206	add	r10, r10, r0		/* r10 <- sym table in FLASH */
207	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
208	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
209	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
210	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
211fixloop:
212	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
213	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
214	ldr	r1, [r2, #4]
215	and	r7, r1, #0xff
216	cmp	r7, #23			/* relative fixup? */
217	beq	fixrel
218	cmp	r7, #2			/* absolute fixup? */
219	beq	fixabs
220	/* ignore unknown type of fixup */
221	b	fixnext
222fixabs:
223	/* absolute fix: set location to (offset) symbol value */
224	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
225	add	r1, r10, r1		/* r1 <- address of symbol in table */
226	ldr	r1, [r1, #4]		/* r1 <- symbol value */
227	add	r1, r1, r9		/* r1 <- relocated sym addr */
228	b	fixnext
229fixrel:
230	/* relative fix: increase location by offset */
231	ldr	r1, [r0]
232	add	r1, r1, r9
233fixnext:
234	str	r1, [r0]
235	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
236	cmp	r2, r3
237	blo	fixloop
238	bx	lr
239
240#endif
241
242relocate_done:
243
244	bx	lr
245
246#ifndef CONFIG_SPL_BUILD
247
248_rel_dyn_start_ofs:
249	.word __rel_dyn_start - _start
250_rel_dyn_end_ofs:
251	.word __rel_dyn_end - _start
252_dynsym_start_ofs:
253	.word __dynsym_start - _start
254
255#endif
256
257	.globl	c_runtime_cpu_setup
258c_runtime_cpu_setup:
259
260	bx	lr
261
262/*
263 *************************************************************************
264 *
265 * CPU_init_critical registers
266 *
267 * setup important registers
268 * setup memory timing
269 *
270 *************************************************************************
271 */
272#ifndef CONFIG_SKIP_LOWLEVEL_INIT
273cpu_init_crit:
274	/*
275	 * flush v4 I/D caches
276	 */
277	mov	r0, #0
278	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
279	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
280
281	/*
282	 * disable MMU stuff and caches
283	 */
284	mrc	p15, 0, r0, c1, c0, 0
285	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
286	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
287	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
288	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
289	mcr	p15, 0, r0, c1, c0, 0
290
291	/*
292	 * Jump to board specific initialization... The Mask ROM will have already initialized
293	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
294	 */
295	mov	ip, lr		/* persevere link reg across call */
296	bl	lowlevel_init	/* go setup pll,mux,memory */
297	mov	lr, ip		/* restore link */
298	mov	pc, lr		/* back to my caller */
299#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
300
301#ifndef CONFIG_SPL_BUILD
302/*
303 *************************************************************************
304 *
305 * Interrupt handling
306 *
307 *************************************************************************
308 */
309@
310@ IRQ stack frame.
311@
312#define S_FRAME_SIZE	72
313
314#define S_OLD_R0	68
315#define S_PSR		64
316#define S_PC		60
317#define S_LR		56
318#define S_SP		52
319
320#define S_IP		48
321#define S_FP		44
322#define S_R10		40
323#define S_R9		36
324#define S_R8		32
325#define S_R7		28
326#define S_R6		24
327#define S_R5		20
328#define S_R4		16
329#define S_R3		12
330#define S_R2		8
331#define S_R1		4
332#define S_R0		0
333
334#define MODE_SVC 0x13
335#define I_BIT	 0x80
336
337/*
338 * use bad_save_user_regs for abort/prefetch/undef/swi ...
339 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
340 */
341
342	.macro	bad_save_user_regs
343	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
344	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
345
346	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
347	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
348	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
349
350	add	r5, sp, #S_SP
351	mov	r1, lr
352	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
353	mov	r0, sp				@ save current stack into r0 (param register)
354	.endm
355
356	.macro	irq_save_user_regs
357	sub	sp, sp, #S_FRAME_SIZE
358	stmia	sp, {r0 - r12}			@ Calling r0-r12
359	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
360	stmdb	r8, {sp, lr}^			@ Calling SP, LR
361	str	lr, [r8, #0]			@ Save calling PC
362	mrs	r6, spsr
363	str	r6, [r8, #4]			@ Save CPSR
364	str	r0, [r8, #8]			@ Save OLD_R0
365	mov	r0, sp
366	.endm
367
368	.macro	irq_restore_user_regs
369	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
370	mov	r0, r0
371	ldr	lr, [sp, #S_PC]			@ Get PC
372	add	sp, sp, #S_FRAME_SIZE
373	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
374	.endm
375
376	.macro get_bad_stack
377	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
378
379	str	lr, [r13]			@ save caller lr in position 0 of saved stack
380	mrs	lr, spsr			@ get the spsr
381	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
382
383	mov	r13, #MODE_SVC			@ prepare SVC-Mode
384	@ msr	spsr_c, r13
385	msr	spsr, r13			@ switch modes, make sure moves will execute
386	mov	lr, pc				@ capture return pc
387	movs	pc, lr				@ jump to next instruction & switch modes.
388	.endm
389
390	.macro get_bad_stack_swi
391	sub	r13, r13, #4			@ space on current stack for scratch reg.
392	str	r0, [r13]			@ save R0's value.
393	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
394	str	lr, [r0]			@ save caller lr in position 0 of saved stack
395	mrs	r0, spsr			@ get the spsr
396	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
397	ldr	r0, [r13]			@ restore r0
398	add	r13, r13, #4			@ pop stack entry
399	.endm
400
401	.macro get_irq_stack			@ setup IRQ stack
402	ldr	sp, IRQ_STACK_START
403	.endm
404
405	.macro get_fiq_stack			@ setup FIQ stack
406	ldr	sp, FIQ_STACK_START
407	.endm
408#endif	/* CONFIG_SPL_BUILD */
409
410/*
411 * exception handlers
412 */
413#ifdef CONFIG_SPL_BUILD
414	.align	5
415do_hang:
416	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
417	bl	hang				/* hang and never return */
418#else	/* !CONFIG_SPL_BUILD */
419	.align	5
420undefined_instruction:
421	get_bad_stack
422	bad_save_user_regs
423	bl	do_undefined_instruction
424
425	.align	5
426software_interrupt:
427	get_bad_stack_swi
428	bad_save_user_regs
429	bl	do_software_interrupt
430
431	.align	5
432prefetch_abort:
433	get_bad_stack
434	bad_save_user_regs
435	bl	do_prefetch_abort
436
437	.align	5
438data_abort:
439	get_bad_stack
440	bad_save_user_regs
441	bl	do_data_abort
442
443	.align	5
444not_used:
445	get_bad_stack
446	bad_save_user_regs
447	bl	do_not_used
448
449#ifdef CONFIG_USE_IRQ
450
451	.align	5
452irq:
453	get_irq_stack
454	irq_save_user_regs
455	bl	do_irq
456	irq_restore_user_regs
457
458	.align	5
459fiq:
460	get_fiq_stack
461	/* someone ought to write a more effiction fiq_save_user_regs */
462	irq_save_user_regs
463	bl	do_fiq
464	irq_restore_user_regs
465
466#else
467
468	.align	5
469irq:
470	get_bad_stack
471	bad_save_user_regs
472	bl	do_irq
473
474	.align	5
475fiq:
476	get_bad_stack
477	bad_save_user_regs
478	bl	do_fiq
479
480#endif
481	.align 5
482.global arm1136_cache_flush
483arm1136_cache_flush:
484#if !defined(CONFIG_SYS_ICACHE_OFF)
485		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
486#endif
487#if !defined(CONFIG_SYS_DCACHE_OFF)
488		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
489#endif
490		mov	pc, lr			@ back to caller
491#endif	/* CONFIG_SPL_BUILD */
492