1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.global _image_copy_end_ofs 104_image_copy_end_ofs: 105 .word __image_copy_end - _start 106 107.globl _bss_end_ofs 108_bss_end_ofs: 109 .word __bss_end__ - _start 110 111.globl _end_ofs 112_end_ofs: 113 .word _end - _start 114 115#ifdef CONFIG_USE_IRQ 116/* IRQ stack memory (calculated at run-time) */ 117.globl IRQ_STACK_START 118IRQ_STACK_START: 119 .word 0x0badc0de 120 121/* IRQ stack memory (calculated at run-time) */ 122.globl FIQ_STACK_START 123FIQ_STACK_START: 124 .word 0x0badc0de 125#endif 126 127/* IRQ stack memory (calculated at run-time) + 8 bytes */ 128.globl IRQ_STACK_START_IN 129IRQ_STACK_START_IN: 130 .word 0x0badc0de 131 132/* 133 * the actual reset code 134 */ 135 136reset: 137 /* 138 * set the cpu to SVC32 mode 139 */ 140 mrs r0,cpsr 141 bic r0,r0,#0x1f 142 orr r0,r0,#0xd3 143 msr cpsr,r0 144 145#ifdef CONFIG_OMAP2420H4 146 /* Copy vectors to mask ROM indirect addr */ 147 adr r0, _start /* r0 <- current position of code */ 148 add r0, r0, #4 /* skip reset vector */ 149 mov r2, #64 /* r2 <- size to copy */ 150 add r2, r0, r2 /* r2 <- source end address */ 151 mov r1, #SRAM_OFFSET0 /* build vect addr */ 152 mov r3, #SRAM_OFFSET1 153 add r1, r1, r3 154 mov r3, #SRAM_OFFSET2 155 add r1, r1, r3 156next: 157 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 158 stmia r1!, {r3-r10} /* copy to target address [r1] */ 159 cmp r0, r2 /* until source end address [r2] */ 160 bne next /* loop until equal */ 161 bl cpy_clk_code /* put dpll adjust code behind vectors */ 162#endif 163 /* the mask ROM code should have PLL and others stable */ 164#ifndef CONFIG_SKIP_LOWLEVEL_INIT 165 bl cpu_init_crit 166#endif 167 168/* Set stackpointer in internal RAM to call board_init_f */ 169call_board_init_f: 170 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 171 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 172 ldr r0,=0x00000000 173 174 bl board_init_f 175 176/*------------------------------------------------------------------------------*/ 177 178/* 179 * void relocate_code (addr_sp, gd, addr_moni) 180 * 181 * This "function" does not return, instead it continues in RAM 182 * after relocating the monitor code. 183 * 184 */ 185 .globl relocate_code 186relocate_code: 187 mov r4, r0 /* save addr_sp */ 188 mov r5, r1 /* save addr of gd */ 189 mov r6, r2 /* save addr of destination */ 190 191 /* Set up the stack */ 192stack_setup: 193 mov sp, r4 194 195 adr r0, _start 196 cmp r0, r6 197 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 198 beq clear_bss /* skip relocation */ 199 mov r1, r6 /* r1 <- scratch for copy_loop */ 200 ldr r3, _image_copy_end_ofs 201 add r2, r0, r3 /* r2 <- source end address */ 202 203copy_loop: 204 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 205 stmia r1!, {r9-r10} /* copy to target address [r1] */ 206 cmp r0, r2 /* until source end address [r2] */ 207 blo copy_loop 208 209#ifndef CONFIG_SPL_BUILD 210 /* 211 * fix .rel.dyn relocations 212 */ 213 ldr r0, _TEXT_BASE /* r0 <- Text base */ 214 sub r9, r6, r0 /* r9 <- relocation offset */ 215 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 216 add r10, r10, r0 /* r10 <- sym table in FLASH */ 217 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 218 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 219 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 220 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 221fixloop: 222 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 223 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 224 ldr r1, [r2, #4] 225 and r7, r1, #0xff 226 cmp r7, #23 /* relative fixup? */ 227 beq fixrel 228 cmp r7, #2 /* absolute fixup? */ 229 beq fixabs 230 /* ignore unknown type of fixup */ 231 b fixnext 232fixabs: 233 /* absolute fix: set location to (offset) symbol value */ 234 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 235 add r1, r10, r1 /* r1 <- address of symbol in table */ 236 ldr r1, [r1, #4] /* r1 <- symbol value */ 237 add r1, r1, r9 /* r1 <- relocated sym addr */ 238 b fixnext 239fixrel: 240 /* relative fix: increase location by offset */ 241 ldr r1, [r0] 242 add r1, r1, r9 243fixnext: 244 str r1, [r0] 245 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 246 cmp r2, r3 247 blo fixloop 248 b clear_bss 249 250_rel_dyn_start_ofs: 251 .word __rel_dyn_start - _start 252_rel_dyn_end_ofs: 253 .word __rel_dyn_end - _start 254_dynsym_start_ofs: 255 .word __dynsym_start - _start 256#endif 257 258clear_bss: 259#ifdef CONFIG_SPL_BUILD 260 /* No relocation for SPL */ 261 ldr r0, =__bss_start 262 ldr r1, =__bss_end__ 263#else 264 ldr r0, _bss_start_ofs 265 ldr r1, _bss_end_ofs 266 mov r4, r6 /* reloc addr */ 267 add r0, r0, r4 268 add r1, r1, r4 269#endif 270 mov r2, #0x00000000 /* clear */ 271 272clbss_l:cmp r0, r1 /* clear loop... */ 273 bhs clbss_e /* if reached end of bss, exit */ 274 str r2, [r0] 275 add r0, r0, #4 276 b clbss_l 277clbss_e: 278 279/* 280 * We are done. Do not return, instead branch to second part of board 281 * initialization, now running from RAM. 282 */ 283#ifdef CONFIG_NAND_SPL 284 ldr r0, _nand_boot_ofs 285 mov pc, r0 286 287_nand_boot_ofs: 288 .word nand_boot 289#else 290jump_2_ram: 291 ldr r0, _board_init_r_ofs 292 adr r1, _start 293 add lr, r0, r1 294 add lr, lr, r9 295 /* setup parameters for board_init_r */ 296 mov r0, r5 /* gd_t */ 297 mov r1, r6 /* dest_addr */ 298 /* jump to it ... */ 299 mov pc, lr 300 301_board_init_r_ofs: 302 .word board_init_r - _start 303#endif 304 305/* 306 ************************************************************************* 307 * 308 * CPU_init_critical registers 309 * 310 * setup important registers 311 * setup memory timing 312 * 313 ************************************************************************* 314 */ 315#ifndef CONFIG_SKIP_LOWLEVEL_INIT 316cpu_init_crit: 317 /* 318 * flush v4 I/D caches 319 */ 320 mov r0, #0 321 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 322 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 323 324 /* 325 * disable MMU stuff and caches 326 */ 327 mrc p15, 0, r0, c1, c0, 0 328 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 329 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 330 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 331 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 332 mcr p15, 0, r0, c1, c0, 0 333 334 /* 335 * Jump to board specific initialization... The Mask ROM will have already initialized 336 * basic memory. Go here to bump up clock rate and handle wake up conditions. 337 */ 338 mov ip, lr /* persevere link reg across call */ 339 bl lowlevel_init /* go setup pll,mux,memory */ 340 mov lr, ip /* restore link */ 341 mov pc, lr /* back to my caller */ 342#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 343 344#ifndef CONFIG_SPL_BUILD 345/* 346 ************************************************************************* 347 * 348 * Interrupt handling 349 * 350 ************************************************************************* 351 */ 352@ 353@ IRQ stack frame. 354@ 355#define S_FRAME_SIZE 72 356 357#define S_OLD_R0 68 358#define S_PSR 64 359#define S_PC 60 360#define S_LR 56 361#define S_SP 52 362 363#define S_IP 48 364#define S_FP 44 365#define S_R10 40 366#define S_R9 36 367#define S_R8 32 368#define S_R7 28 369#define S_R6 24 370#define S_R5 20 371#define S_R4 16 372#define S_R3 12 373#define S_R2 8 374#define S_R1 4 375#define S_R0 0 376 377#define MODE_SVC 0x13 378#define I_BIT 0x80 379 380/* 381 * use bad_save_user_regs for abort/prefetch/undef/swi ... 382 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 383 */ 384 385 .macro bad_save_user_regs 386 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 387 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 388 389 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 390 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 391 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 392 393 add r5, sp, #S_SP 394 mov r1, lr 395 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 396 mov r0, sp @ save current stack into r0 (param register) 397 .endm 398 399 .macro irq_save_user_regs 400 sub sp, sp, #S_FRAME_SIZE 401 stmia sp, {r0 - r12} @ Calling r0-r12 402 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 403 stmdb r8, {sp, lr}^ @ Calling SP, LR 404 str lr, [r8, #0] @ Save calling PC 405 mrs r6, spsr 406 str r6, [r8, #4] @ Save CPSR 407 str r0, [r8, #8] @ Save OLD_R0 408 mov r0, sp 409 .endm 410 411 .macro irq_restore_user_regs 412 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 413 mov r0, r0 414 ldr lr, [sp, #S_PC] @ Get PC 415 add sp, sp, #S_FRAME_SIZE 416 subs pc, lr, #4 @ return & move spsr_svc into cpsr 417 .endm 418 419 .macro get_bad_stack 420 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 421 422 str lr, [r13] @ save caller lr in position 0 of saved stack 423 mrs lr, spsr @ get the spsr 424 str lr, [r13, #4] @ save spsr in position 1 of saved stack 425 426 mov r13, #MODE_SVC @ prepare SVC-Mode 427 @ msr spsr_c, r13 428 msr spsr, r13 @ switch modes, make sure moves will execute 429 mov lr, pc @ capture return pc 430 movs pc, lr @ jump to next instruction & switch modes. 431 .endm 432 433 .macro get_bad_stack_swi 434 sub r13, r13, #4 @ space on current stack for scratch reg. 435 str r0, [r13] @ save R0's value. 436 ldr r0, IRQ_STACK_START_IN @ get data regions start 437 str lr, [r0] @ save caller lr in position 0 of saved stack 438 mrs r0, spsr @ get the spsr 439 str lr, [r0, #4] @ save spsr in position 1 of saved stack 440 ldr r0, [r13] @ restore r0 441 add r13, r13, #4 @ pop stack entry 442 .endm 443 444 .macro get_irq_stack @ setup IRQ stack 445 ldr sp, IRQ_STACK_START 446 .endm 447 448 .macro get_fiq_stack @ setup FIQ stack 449 ldr sp, FIQ_STACK_START 450 .endm 451#endif /* CONFIG_SPL_BUILD */ 452 453/* 454 * exception handlers 455 */ 456#ifdef CONFIG_SPL_BUILD 457 .align 5 458do_hang: 459 ldr sp, _TEXT_BASE /* use 32 words about stack */ 460 bl hang /* hang and never return */ 461#else /* !CONFIG_SPL_BUILD */ 462 .align 5 463undefined_instruction: 464 get_bad_stack 465 bad_save_user_regs 466 bl do_undefined_instruction 467 468 .align 5 469software_interrupt: 470 get_bad_stack_swi 471 bad_save_user_regs 472 bl do_software_interrupt 473 474 .align 5 475prefetch_abort: 476 get_bad_stack 477 bad_save_user_regs 478 bl do_prefetch_abort 479 480 .align 5 481data_abort: 482 get_bad_stack 483 bad_save_user_regs 484 bl do_data_abort 485 486 .align 5 487not_used: 488 get_bad_stack 489 bad_save_user_regs 490 bl do_not_used 491 492#ifdef CONFIG_USE_IRQ 493 494 .align 5 495irq: 496 get_irq_stack 497 irq_save_user_regs 498 bl do_irq 499 irq_restore_user_regs 500 501 .align 5 502fiq: 503 get_fiq_stack 504 /* someone ought to write a more effiction fiq_save_user_regs */ 505 irq_save_user_regs 506 bl do_fiq 507 irq_restore_user_regs 508 509#else 510 511 .align 5 512irq: 513 get_bad_stack 514 bad_save_user_regs 515 bl do_irq 516 517 .align 5 518fiq: 519 get_bad_stack 520 bad_save_user_regs 521 bl do_fiq 522 523#endif 524 .align 5 525.global arm1136_cache_flush 526arm1136_cache_flush: 527#if !defined(CONFIG_SYS_ICACHE_OFF) 528 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 529#endif 530#if !defined(CONFIG_SYS_DCACHE_OFF) 531 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 532#endif 533 mov pc, lr @ back to caller 534#endif /* CONFIG_SPL_BUILD */ 535