xref: /openbmc/u-boot/arch/arm/cpu/arm1136/start.S (revision 67cd4a63487400317f1586b130bc2475767a5315)
1/*
2 *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
3 *
4 *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
5 *
6 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
7 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
8 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
9 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
10 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <asm-offsets.h>
32#include <config.h>
33#include <version.h>
34.globl _start
35_start: b	reset
36#ifdef CONFIG_SPL_BUILD
37	ldr	pc, _hang
38	ldr	pc, _hang
39	ldr	pc, _hang
40	ldr	pc, _hang
41	ldr	pc, _hang
42	ldr	pc, _hang
43	ldr	pc, _hang
44
45_hang:
46	.word	do_hang
47	.word	0x12345678
48	.word	0x12345678
49	.word	0x12345678
50	.word	0x12345678
51	.word	0x12345678
52	.word	0x12345678
53	.word	0x12345678	/* now 16*4=64 */
54#else
55	ldr	pc, _undefined_instruction
56	ldr	pc, _software_interrupt
57	ldr	pc, _prefetch_abort
58	ldr	pc, _data_abort
59	ldr	pc, _not_used
60	ldr	pc, _irq
61	ldr	pc, _fiq
62
63_undefined_instruction: .word undefined_instruction
64_software_interrupt:	.word software_interrupt
65_prefetch_abort:	.word prefetch_abort
66_data_abort:		.word data_abort
67_not_used:		.word not_used
68_irq:			.word irq
69_fiq:			.word fiq
70_pad:			.word 0x12345678 /* now 16*4=64 */
71#endif	/* CONFIG_SPL_BUILD */
72.global _end_vect
73_end_vect:
74
75	.balignl 16,0xdeadbeef
76/*
77 *************************************************************************
78 *
79 * Startup Code (reset vector)
80 *
81 * do important init only if we don't start from memory!
82 * setup Memory and board specific bits prior to relocation.
83 * relocate armboot to ram
84 * setup stack
85 *
86 *************************************************************************
87 */
88
89.globl _TEXT_BASE
90_TEXT_BASE:
91#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
92	.word	CONFIG_SPL_TEXT_BASE
93#else
94	.word	CONFIG_SYS_TEXT_BASE
95#endif
96
97/*
98 * These are defined in the board-specific linker script.
99 * Subtracting _start from them lets the linker put their
100 * relative position in the executable instead of leaving
101 * them null.
102 */
103.globl _bss_start_ofs
104_bss_start_ofs:
105	.word __bss_start - _start
106
107.globl _bss_end_ofs
108_bss_end_ofs:
109	.word __bss_end - _start
110
111.globl _end_ofs
112_end_ofs:
113	.word _end - _start
114
115#ifdef CONFIG_USE_IRQ
116/* IRQ stack memory (calculated at run-time) */
117.globl IRQ_STACK_START
118IRQ_STACK_START:
119	.word	0x0badc0de
120
121/* IRQ stack memory (calculated at run-time) */
122.globl FIQ_STACK_START
123FIQ_STACK_START:
124	.word 0x0badc0de
125#endif
126
127/* IRQ stack memory (calculated at run-time) + 8 bytes */
128.globl IRQ_STACK_START_IN
129IRQ_STACK_START_IN:
130	.word	0x0badc0de
131
132/*
133 * the actual reset code
134 */
135
136reset:
137	/*
138	 * set the cpu to SVC32 mode
139	 */
140	mrs	r0,cpsr
141	bic	r0,r0,#0x1f
142	orr	r0,r0,#0xd3
143	msr	cpsr,r0
144
145#ifdef CONFIG_OMAP2420H4
146       /* Copy vectors to mask ROM indirect addr */
147	adr	r0, _start		/* r0 <- current position of code   */
148		add     r0, r0, #4				/* skip reset vector			*/
149	mov	r2, #64			/* r2 <- size to copy  */
150	add	r2, r0, r2		/* r2 <- source end address	    */
151	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
152	mov	r3, #SRAM_OFFSET1
153	add	r1, r1, r3
154	mov	r3, #SRAM_OFFSET2
155	add	r1, r1, r3
156next:
157	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
158	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
159	cmp	r0, r2			/* until source end address [r2]    */
160	bne	next			/* loop until equal */
161	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
162#endif
163	/* the mask ROM code should have PLL and others stable */
164#ifndef CONFIG_SKIP_LOWLEVEL_INIT
165	bl  cpu_init_crit
166#endif
167
168	bl	_main
169
170/*------------------------------------------------------------------------------*/
171
172	.globl	c_runtime_cpu_setup
173c_runtime_cpu_setup:
174
175	bx	lr
176
177/*
178 *************************************************************************
179 *
180 * CPU_init_critical registers
181 *
182 * setup important registers
183 * setup memory timing
184 *
185 *************************************************************************
186 */
187#ifndef CONFIG_SKIP_LOWLEVEL_INIT
188cpu_init_crit:
189	/*
190	 * flush v4 I/D caches
191	 */
192	mov	r0, #0
193	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
194	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
195
196	/*
197	 * disable MMU stuff and caches
198	 */
199	mrc	p15, 0, r0, c1, c0, 0
200	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
201	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
202	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
203	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
204	mcr	p15, 0, r0, c1, c0, 0
205
206	/*
207	 * Jump to board specific initialization... The Mask ROM will have already initialized
208	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
209	 */
210	mov	ip, lr		/* persevere link reg across call */
211	bl	lowlevel_init	/* go setup pll,mux,memory */
212	mov	lr, ip		/* restore link */
213	mov	pc, lr		/* back to my caller */
214#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
215
216#ifndef CONFIG_SPL_BUILD
217/*
218 *************************************************************************
219 *
220 * Interrupt handling
221 *
222 *************************************************************************
223 */
224@
225@ IRQ stack frame.
226@
227#define S_FRAME_SIZE	72
228
229#define S_OLD_R0	68
230#define S_PSR		64
231#define S_PC		60
232#define S_LR		56
233#define S_SP		52
234
235#define S_IP		48
236#define S_FP		44
237#define S_R10		40
238#define S_R9		36
239#define S_R8		32
240#define S_R7		28
241#define S_R6		24
242#define S_R5		20
243#define S_R4		16
244#define S_R3		12
245#define S_R2		8
246#define S_R1		4
247#define S_R0		0
248
249#define MODE_SVC 0x13
250#define I_BIT	 0x80
251
252/*
253 * use bad_save_user_regs for abort/prefetch/undef/swi ...
254 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
255 */
256
257	.macro	bad_save_user_regs
258	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
259	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
260
261	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
262	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
263	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
264
265	add	r5, sp, #S_SP
266	mov	r1, lr
267	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
268	mov	r0, sp				@ save current stack into r0 (param register)
269	.endm
270
271	.macro	irq_save_user_regs
272	sub	sp, sp, #S_FRAME_SIZE
273	stmia	sp, {r0 - r12}			@ Calling r0-r12
274	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
275	stmdb	r8, {sp, lr}^			@ Calling SP, LR
276	str	lr, [r8, #0]			@ Save calling PC
277	mrs	r6, spsr
278	str	r6, [r8, #4]			@ Save CPSR
279	str	r0, [r8, #8]			@ Save OLD_R0
280	mov	r0, sp
281	.endm
282
283	.macro	irq_restore_user_regs
284	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
285	mov	r0, r0
286	ldr	lr, [sp, #S_PC]			@ Get PC
287	add	sp, sp, #S_FRAME_SIZE
288	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
289	.endm
290
291	.macro get_bad_stack
292	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
293
294	str	lr, [r13]			@ save caller lr in position 0 of saved stack
295	mrs	lr, spsr			@ get the spsr
296	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
297
298	mov	r13, #MODE_SVC			@ prepare SVC-Mode
299	@ msr	spsr_c, r13
300	msr	spsr, r13			@ switch modes, make sure moves will execute
301	mov	lr, pc				@ capture return pc
302	movs	pc, lr				@ jump to next instruction & switch modes.
303	.endm
304
305	.macro get_bad_stack_swi
306	sub	r13, r13, #4			@ space on current stack for scratch reg.
307	str	r0, [r13]			@ save R0's value.
308	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
309	str	lr, [r0]			@ save caller lr in position 0 of saved stack
310	mrs	lr, spsr			@ get the spsr
311	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
312	ldr	lr, [r0]			@ restore lr
313	ldr	r0, [r13]			@ restore r0
314	add	r13, r13, #4			@ pop stack entry
315	.endm
316
317	.macro get_irq_stack			@ setup IRQ stack
318	ldr	sp, IRQ_STACK_START
319	.endm
320
321	.macro get_fiq_stack			@ setup FIQ stack
322	ldr	sp, FIQ_STACK_START
323	.endm
324#endif	/* CONFIG_SPL_BUILD */
325
326/*
327 * exception handlers
328 */
329#ifdef CONFIG_SPL_BUILD
330	.align	5
331do_hang:
332	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
333	bl	hang				/* hang and never return */
334#else	/* !CONFIG_SPL_BUILD */
335	.align	5
336undefined_instruction:
337	get_bad_stack
338	bad_save_user_regs
339	bl	do_undefined_instruction
340
341	.align	5
342software_interrupt:
343	get_bad_stack_swi
344	bad_save_user_regs
345	bl	do_software_interrupt
346
347	.align	5
348prefetch_abort:
349	get_bad_stack
350	bad_save_user_regs
351	bl	do_prefetch_abort
352
353	.align	5
354data_abort:
355	get_bad_stack
356	bad_save_user_regs
357	bl	do_data_abort
358
359	.align	5
360not_used:
361	get_bad_stack
362	bad_save_user_regs
363	bl	do_not_used
364
365#ifdef CONFIG_USE_IRQ
366
367	.align	5
368irq:
369	get_irq_stack
370	irq_save_user_regs
371	bl	do_irq
372	irq_restore_user_regs
373
374	.align	5
375fiq:
376	get_fiq_stack
377	/* someone ought to write a more effiction fiq_save_user_regs */
378	irq_save_user_regs
379	bl	do_fiq
380	irq_restore_user_regs
381
382#else
383
384	.align	5
385irq:
386	get_bad_stack
387	bad_save_user_regs
388	bl	do_irq
389
390	.align	5
391fiq:
392	get_bad_stack
393	bad_save_user_regs
394	bl	do_fiq
395
396#endif
397	.align 5
398.global arm1136_cache_flush
399arm1136_cache_flush:
400#if !defined(CONFIG_SYS_ICACHE_OFF)
401		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
402#endif
403#if !defined(CONFIG_SYS_DCACHE_OFF)
404		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
405#endif
406		mov	pc, lr			@ back to caller
407#endif	/* CONFIG_SPL_BUILD */
408