1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_PRELOADER 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_PRELOADER */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word _end - _start 106 107#ifdef CONFIG_USE_IRQ 108/* IRQ stack memory (calculated at run-time) */ 109.globl IRQ_STACK_START 110IRQ_STACK_START: 111 .word 0x0badc0de 112 113/* IRQ stack memory (calculated at run-time) */ 114.globl FIQ_STACK_START 115FIQ_STACK_START: 116 .word 0x0badc0de 117#endif 118 119/* IRQ stack memory (calculated at run-time) + 8 bytes */ 120.globl IRQ_STACK_START_IN 121IRQ_STACK_START_IN: 122 .word 0x0badc0de 123 124/* 125 * the actual reset code 126 */ 127 128reset: 129 /* 130 * set the cpu to SVC32 mode 131 */ 132 mrs r0,cpsr 133 bic r0,r0,#0x1f 134 orr r0,r0,#0xd3 135 msr cpsr,r0 136 137#ifdef CONFIG_OMAP2420H4 138 /* Copy vectors to mask ROM indirect addr */ 139 adr r0, _start /* r0 <- current position of code */ 140 add r0, r0, #4 /* skip reset vector */ 141 mov r2, #64 /* r2 <- size to copy */ 142 add r2, r0, r2 /* r2 <- source end address */ 143 mov r1, #SRAM_OFFSET0 /* build vect addr */ 144 mov r3, #SRAM_OFFSET1 145 add r1, r1, r3 146 mov r3, #SRAM_OFFSET2 147 add r1, r1, r3 148next: 149 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 150 stmia r1!, {r3-r10} /* copy to target address [r1] */ 151 cmp r0, r2 /* until source end address [r2] */ 152 bne next /* loop until equal */ 153 bl cpy_clk_code /* put dpll adjust code behind vectors */ 154#endif 155 /* the mask ROM code should have PLL and others stable */ 156#ifndef CONFIG_SKIP_LOWLEVEL_INIT 157 bl cpu_init_crit 158#endif 159 160/* Set stackpointer in internal RAM to call board_init_f */ 161call_board_init_f: 162 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 163 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 164 ldr r0,=0x00000000 165 166#ifdef CONFIG_NAND_SPL 167 bl nand_boot 168#else 169#ifdef CONFIG_ONENAND_IPL 170 bl start_oneboot 171#else 172 bl board_init_f 173#endif /* CONFIG_ONENAND_IPL */ 174#endif /* CONFIG_NAND_SPL */ 175 176/*------------------------------------------------------------------------------*/ 177 178/* 179 * void relocate_code (addr_sp, gd, addr_moni) 180 * 181 * This "function" does not return, instead it continues in RAM 182 * after relocating the monitor code. 183 * 184 */ 185 .globl relocate_code 186relocate_code: 187 mov r4, r0 /* save addr_sp */ 188 mov r5, r1 /* save addr of gd */ 189 mov r6, r2 /* save addr of destination */ 190 191 /* Set up the stack */ 192stack_setup: 193 mov sp, r4 194 195 adr r0, _start 196 cmp r0, r6 197 beq clear_bss /* skip relocation */ 198 mov r1, r6 /* r1 <- scratch for copy_loop */ 199 ldr r2, _TEXT_BASE 200 ldr r3, _bss_start_ofs 201 add r2, r0, r3 /* r2 <- source end address */ 202 203copy_loop: 204 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 205 stmia r1!, {r9-r10} /* copy to target address [r1] */ 206 cmp r0, r2 /* until source end address [r2] */ 207 blo copy_loop 208 209#ifndef CONFIG_PRELOADER 210 /* 211 * fix .rel.dyn relocations 212 */ 213 ldr r0, _TEXT_BASE /* r0 <- Text base */ 214 sub r9, r6, r0 /* r9 <- relocation offset */ 215 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 216 add r10, r10, r0 /* r10 <- sym table in FLASH */ 217 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 218 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 219 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 220 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 221fixloop: 222 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 223 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 224 ldr r1, [r2, #4] 225 and r7, r1, #0xff 226 cmp r7, #23 /* relative fixup? */ 227 beq fixrel 228 cmp r7, #2 /* absolute fixup? */ 229 beq fixabs 230 /* ignore unknown type of fixup */ 231 b fixnext 232fixabs: 233 /* absolute fix: set location to (offset) symbol value */ 234 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 235 add r1, r10, r1 /* r1 <- address of symbol in table */ 236 ldr r1, [r1, #4] /* r1 <- symbol value */ 237 add r1, r1, r9 /* r1 <- relocated sym addr */ 238 b fixnext 239fixrel: 240 /* relative fix: increase location by offset */ 241 ldr r1, [r0] 242 add r1, r1, r9 243fixnext: 244 str r1, [r0] 245 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 246 cmp r2, r3 247 blo fixloop 248#endif 249 250clear_bss: 251#ifndef CONFIG_PRELOADER 252 ldr r0, _bss_start_ofs 253 ldr r1, _bss_end_ofs 254 ldr r3, _TEXT_BASE /* Text base */ 255 mov r4, r6 /* reloc addr */ 256 add r0, r0, r4 257 add r1, r1, r4 258 mov r2, #0x00000000 /* clear */ 259 260clbss_l:str r2, [r0] /* clear loop... */ 261 add r0, r0, #4 262 cmp r0, r1 263 bne clbss_l 264#endif /* #ifndef CONFIG_PRELOADER */ 265 266/* 267 * We are done. Do not return, instead branch to second part of board 268 * initialization, now running from RAM. 269 */ 270#ifdef CONFIG_NAND_SPL 271 ldr r0, _nand_boot_ofs 272 adr r1, _start 273 add pc, r0, r1 274_nand_boot_ofs 275 : .word nand_boot - _start 276#else 277jump_2_ram: 278 ldr r0, _board_init_r_ofs 279 adr r1, _start 280 add lr, r0, r1 281 add lr, lr, r9 282 /* setup parameters for board_init_r */ 283 mov r0, r5 /* gd_t */ 284 mov r1, r6 /* dest_addr */ 285 /* jump to it ... */ 286 mov pc, lr 287 288_board_init_r_ofs: 289 .word board_init_r - _start 290#endif 291 292_rel_dyn_start_ofs: 293 .word __rel_dyn_start - _start 294_rel_dyn_end_ofs: 295 .word __rel_dyn_end - _start 296_dynsym_start_ofs: 297 .word __dynsym_start - _start 298 299/* 300 ************************************************************************* 301 * 302 * CPU_init_critical registers 303 * 304 * setup important registers 305 * setup memory timing 306 * 307 ************************************************************************* 308 */ 309#ifndef CONFIG_SKIP_LOWLEVEL_INIT 310cpu_init_crit: 311 /* 312 * flush v4 I/D caches 313 */ 314 mov r0, #0 315 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 316 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 317 318 /* 319 * disable MMU stuff and caches 320 */ 321 mrc p15, 0, r0, c1, c0, 0 322 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 323 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 324 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 325 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 326 mcr p15, 0, r0, c1, c0, 0 327 328 /* 329 * Jump to board specific initialization... The Mask ROM will have already initialized 330 * basic memory. Go here to bump up clock rate and handle wake up conditions. 331 */ 332 mov ip, lr /* persevere link reg across call */ 333 bl lowlevel_init /* go setup pll,mux,memory */ 334 mov lr, ip /* restore link */ 335 mov pc, lr /* back to my caller */ 336#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 337 338#ifndef CONFIG_PRELOADER 339/* 340 ************************************************************************* 341 * 342 * Interrupt handling 343 * 344 ************************************************************************* 345 */ 346@ 347@ IRQ stack frame. 348@ 349#define S_FRAME_SIZE 72 350 351#define S_OLD_R0 68 352#define S_PSR 64 353#define S_PC 60 354#define S_LR 56 355#define S_SP 52 356 357#define S_IP 48 358#define S_FP 44 359#define S_R10 40 360#define S_R9 36 361#define S_R8 32 362#define S_R7 28 363#define S_R6 24 364#define S_R5 20 365#define S_R4 16 366#define S_R3 12 367#define S_R2 8 368#define S_R1 4 369#define S_R0 0 370 371#define MODE_SVC 0x13 372#define I_BIT 0x80 373 374/* 375 * use bad_save_user_regs for abort/prefetch/undef/swi ... 376 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 377 */ 378 379 .macro bad_save_user_regs 380 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 381 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 382 383 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 384 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 385 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 386 387 add r5, sp, #S_SP 388 mov r1, lr 389 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 390 mov r0, sp @ save current stack into r0 (param register) 391 .endm 392 393 .macro irq_save_user_regs 394 sub sp, sp, #S_FRAME_SIZE 395 stmia sp, {r0 - r12} @ Calling r0-r12 396 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 397 stmdb r8, {sp, lr}^ @ Calling SP, LR 398 str lr, [r8, #0] @ Save calling PC 399 mrs r6, spsr 400 str r6, [r8, #4] @ Save CPSR 401 str r0, [r8, #8] @ Save OLD_R0 402 mov r0, sp 403 .endm 404 405 .macro irq_restore_user_regs 406 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 407 mov r0, r0 408 ldr lr, [sp, #S_PC] @ Get PC 409 add sp, sp, #S_FRAME_SIZE 410 subs pc, lr, #4 @ return & move spsr_svc into cpsr 411 .endm 412 413 .macro get_bad_stack 414 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 415 416 str lr, [r13] @ save caller lr in position 0 of saved stack 417 mrs lr, spsr @ get the spsr 418 str lr, [r13, #4] @ save spsr in position 1 of saved stack 419 420 mov r13, #MODE_SVC @ prepare SVC-Mode 421 @ msr spsr_c, r13 422 msr spsr, r13 @ switch modes, make sure moves will execute 423 mov lr, pc @ capture return pc 424 movs pc, lr @ jump to next instruction & switch modes. 425 .endm 426 427 .macro get_bad_stack_swi 428 sub r13, r13, #4 @ space on current stack for scratch reg. 429 str r0, [r13] @ save R0's value. 430 ldr r0, IRQ_STACK_START_IN @ get data regions start 431 str lr, [r0] @ save caller lr in position 0 of saved stack 432 mrs r0, spsr @ get the spsr 433 str lr, [r0, #4] @ save spsr in position 1 of saved stack 434 ldr r0, [r13] @ restore r0 435 add r13, r13, #4 @ pop stack entry 436 .endm 437 438 .macro get_irq_stack @ setup IRQ stack 439 ldr sp, IRQ_STACK_START 440 .endm 441 442 .macro get_fiq_stack @ setup FIQ stack 443 ldr sp, FIQ_STACK_START 444 .endm 445#endif /* CONFIG_PRELOADER */ 446 447/* 448 * exception handlers 449 */ 450#ifdef CONFIG_PRELOADER 451 .align 5 452do_hang: 453 ldr sp, _TEXT_BASE /* use 32 words about stack */ 454 bl hang /* hang and never return */ 455#else /* !CONFIG_PRELOADER */ 456 .align 5 457undefined_instruction: 458 get_bad_stack 459 bad_save_user_regs 460 bl do_undefined_instruction 461 462 .align 5 463software_interrupt: 464 get_bad_stack_swi 465 bad_save_user_regs 466 bl do_software_interrupt 467 468 .align 5 469prefetch_abort: 470 get_bad_stack 471 bad_save_user_regs 472 bl do_prefetch_abort 473 474 .align 5 475data_abort: 476 get_bad_stack 477 bad_save_user_regs 478 bl do_data_abort 479 480 .align 5 481not_used: 482 get_bad_stack 483 bad_save_user_regs 484 bl do_not_used 485 486#ifdef CONFIG_USE_IRQ 487 488 .align 5 489irq: 490 get_irq_stack 491 irq_save_user_regs 492 bl do_irq 493 irq_restore_user_regs 494 495 .align 5 496fiq: 497 get_fiq_stack 498 /* someone ought to write a more effiction fiq_save_user_regs */ 499 irq_save_user_regs 500 bl do_fiq 501 irq_restore_user_regs 502 503#else 504 505 .align 5 506irq: 507 get_bad_stack 508 bad_save_user_regs 509 bl do_irq 510 511 .align 5 512fiq: 513 get_bad_stack 514 bad_save_user_regs 515 bl do_fiq 516 517#endif 518 .align 5 519.global arm1136_cache_flush 520arm1136_cache_flush: 521#if !defined(CONFIG_SYS_NO_ICACHE) 522 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 523#endif 524#if !defined(CONFIG_SYS_NO_DCACHE) 525 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 526#endif 527 mov pc, lr @ back to caller 528#endif /* CONFIG_PRELOADER */ 529