1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_PRELOADER 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_PRELOADER */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word _end - _start 106 107.globl _datarel_start_ofs 108_datarel_start_ofs: 109 .word __datarel_start - _start 110 111.globl _datarelrolocal_start_ofs 112_datarelrolocal_start_ofs: 113 .word __datarelrolocal_start - _start 114 115.globl _datarellocal_start_ofs 116_datarellocal_start_ofs: 117 .word __datarellocal_start - _start 118 119.globl _datarelro_start_ofs 120_datarelro_start_ofs: 121 .word __datarelro_start - _start 122 123#ifdef CONFIG_USE_IRQ 124/* IRQ stack memory (calculated at run-time) */ 125.globl IRQ_STACK_START 126IRQ_STACK_START: 127 .word 0x0badc0de 128 129/* IRQ stack memory (calculated at run-time) */ 130.globl FIQ_STACK_START 131FIQ_STACK_START: 132 .word 0x0badc0de 133#endif 134 135#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 136/* IRQ stack memory (calculated at run-time) + 8 bytes */ 137.globl IRQ_STACK_START_IN 138IRQ_STACK_START_IN: 139 .word 0x0badc0de 140#endif 141 142#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 143/* 144 * the actual reset code 145 */ 146 147reset: 148 /* 149 * set the cpu to SVC32 mode 150 */ 151 mrs r0,cpsr 152 bic r0,r0,#0x1f 153 orr r0,r0,#0xd3 154 msr cpsr,r0 155 156#ifdef CONFIG_OMAP2420H4 157 /* Copy vectors to mask ROM indirect addr */ 158 adr r0, _start /* r0 <- current position of code */ 159 add r0, r0, #4 /* skip reset vector */ 160 mov r2, #64 /* r2 <- size to copy */ 161 add r2, r0, r2 /* r2 <- source end address */ 162 mov r1, #SRAM_OFFSET0 /* build vect addr */ 163 mov r3, #SRAM_OFFSET1 164 add r1, r1, r3 165 mov r3, #SRAM_OFFSET2 166 add r1, r1, r3 167next: 168 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 169 stmia r1!, {r3-r10} /* copy to target address [r1] */ 170 cmp r0, r2 /* until source end address [r2] */ 171 bne next /* loop until equal */ 172 bl cpy_clk_code /* put dpll adjust code behind vectors */ 173#endif 174 /* the mask ROM code should have PLL and others stable */ 175#ifndef CONFIG_SKIP_LOWLEVEL_INIT 176 bl cpu_init_crit 177#endif 178 179/* Set stackpointer in internal RAM to call board_init_f */ 180call_board_init_f: 181 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 182 ldr r0,=0x00000000 183 184#ifdef CONFIG_NAND_SPL 185 bl nand_boot 186#else 187#ifdef CONFIG_ONENAND_IPL 188 bl start_oneboot 189#else 190 bl board_init_f 191#endif /* CONFIG_ONENAND_IPL */ 192#endif /* CONFIG_NAND_SPL */ 193 194/*------------------------------------------------------------------------------*/ 195 196/* 197 * void relocate_code (addr_sp, gd, addr_moni) 198 * 199 * This "function" does not return, instead it continues in RAM 200 * after relocating the monitor code. 201 * 202 */ 203 .globl relocate_code 204relocate_code: 205 mov r4, r0 /* save addr_sp */ 206 mov r5, r1 /* save addr of gd */ 207 mov r6, r2 /* save addr of destination */ 208 mov r7, r2 /* save addr of destination */ 209 210 /* Set up the stack */ 211stack_setup: 212 mov sp, r4 213 214 adr r0, _start 215 ldr r2, _TEXT_BASE 216 ldr r3, _bss_start_ofs 217 add r2, r0, r3 /* r2 <- source end address */ 218 cmp r0, r6 219 beq clear_bss 220 221#ifndef CONFIG_SKIP_RELOCATE_UBOOT 222copy_loop: 223 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 224 stmia r6!, {r9-r10} /* copy to target address [r1] */ 225 cmp r0, r2 /* until source end address [r2] */ 226 blo copy_loop 227 228#ifndef CONFIG_PRELOADER 229 /* 230 * fix .rel.dyn relocations 231 */ 232 ldr r0, _TEXT_BASE /* r0 <- Text base */ 233 sub r9, r7, r0 /* r9 <- relocation offset */ 234 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 235 add r10, r10, r0 /* r10 <- sym table in FLASH */ 236 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 237 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 238 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 239 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 240fixloop: 241 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 242 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 243 ldr r1, [r2, #4] 244 and r8, r1, #0xff 245 cmp r8, #23 /* relative fixup? */ 246 beq fixrel 247 cmp r8, #2 /* absolute fixup? */ 248 beq fixabs 249 /* ignore unknown type of fixup */ 250 b fixnext 251fixabs: 252 /* absolute fix: set location to (offset) symbol value */ 253 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 254 add r1, r10, r1 /* r1 <- address of symbol in table */ 255 ldr r1, [r1, #4] /* r1 <- symbol value */ 256 add r1, r9 /* r1 <- relocated sym addr */ 257 b fixnext 258fixrel: 259 /* relative fix: increase location by offset */ 260 ldr r1, [r0] 261 add r1, r1, r9 262fixnext: 263 str r1, [r0] 264 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 265 cmp r2, r3 266 ble fixloop 267#endif 268#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ 269 270clear_bss: 271#ifndef CONFIG_PRELOADER 272 ldr r0, _bss_start_ofs 273 ldr r1, _bss_end_ofs 274 ldr r3, _TEXT_BASE /* Text base */ 275 mov r4, r7 /* reloc addr */ 276 add r0, r0, r4 277 add r1, r1, r4 278 mov r2, #0x00000000 /* clear */ 279 280clbss_l:str r2, [r0] /* clear loop... */ 281 add r0, r0, #4 282 cmp r0, r1 283 bne clbss_l 284#endif /* #ifndef CONFIG_PRELOADER */ 285 286/* 287 * We are done. Do not return, instead branch to second part of board 288 * initialization, now running from RAM. 289 */ 290#ifdef CONFIG_NAND_SPL 291 ldr r0, _nand_boot_ofs 292 adr r1, _start 293 add pc, r0, r1 294_nand_boot_ofs 295 : .word nand_boot - _start 296#else 297jump_2_ram: 298 ldr r0, _board_init_r_ofs 299 adr r1, _start 300 add r0, r0, r1 301 add lr, r0, r9 302 /* setup parameters for board_init_r */ 303 mov r0, r5 /* gd_t */ 304 mov r1, r7 /* dest_addr */ 305 /* jump to it ... */ 306 mov pc, lr 307 308_board_init_r_ofs: 309 .word board_init_r - _start 310#endif 311 312_rel_dyn_start_ofs: 313 .word __rel_dyn_start - _start 314_rel_dyn_end_ofs: 315 .word __rel_dyn_end - _start 316_dynsym_start_ofs: 317 .word __dynsym_start - _start 318 319#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ 320/* 321 * the actual reset code 322 */ 323 324reset: 325 /* 326 * set the cpu to SVC32 mode 327 */ 328 mrs r0,cpsr 329 bic r0,r0,#0x1f 330 orr r0,r0,#0xd3 331 msr cpsr,r0 332 333#ifdef CONFIG_OMAP2420H4 334 /* Copy vectors to mask ROM indirect addr */ 335 adr r0, _start /* r0 <- current position of code */ 336 add r0, r0, #4 /* skip reset vector */ 337 mov r2, #64 /* r2 <- size to copy */ 338 add r2, r0, r2 /* r2 <- source end address */ 339 mov r1, #SRAM_OFFSET0 /* build vect addr */ 340 mov r3, #SRAM_OFFSET1 341 add r1, r1, r3 342 mov r3, #SRAM_OFFSET2 343 add r1, r1, r3 344next: 345 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 346 stmia r1!, {r3-r10} /* copy to target address [r1] */ 347 cmp r0, r2 /* until source end address [r2] */ 348 bne next /* loop until equal */ 349 bl cpy_clk_code /* put dpll adjust code behind vectors */ 350#endif 351 /* the mask ROM code should have PLL and others stable */ 352#ifndef CONFIG_SKIP_LOWLEVEL_INIT 353 bl cpu_init_crit 354#endif 355 356#ifndef CONFIG_SKIP_RELOCATE_UBOOT 357relocate: /* relocate U-Boot to RAM */ 358 adr r0, _start /* r0 <- current position of code */ 359 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ 360 cmp r0, r1 /* don't reloc during debug */ 361#ifndef CONFIG_PRELOADER 362 beq stack_setup 363#endif /* CONFIG_PRELOADER */ 364 365 ldr r2, _armboot_start 366 ldr r3, _bss_start 367 sub r2, r3, r2 /* r2 <- size of armboot */ 368 add r2, r0, r2 /* r2 <- source end address */ 369 370copy_loop: 371 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 372 stmia r1!, {r3-r10} /* copy to target address [r1] */ 373 cmp r0, r2 /* until source end address [r2] */ 374 blo copy_loop 375#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ 376 377 /* Set up the stack */ 378stack_setup: 379 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ 380#ifdef CONFIG_PRELOADER 381 sub sp, r0, #128 /* leave 32 words for abort-stack */ 382#else 383 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ 384 sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */ 385#ifdef CONFIG_USE_IRQ 386 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) 387#endif 388 sub sp, r0, #12 /* leave 3 words for abort-stack */ 389#endif /* CONFIG_PRELOADER */ 390 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 391 392clear_bss: 393 adr r2, _start 394 ldr r0, _bss_start_ofs /* find start of bss segment */ 395 add r0, r0, r2 396 ldr r1, _bss_end_ofs /* stop here */ 397 add r1, r1, r2 398 mov r2, #0x00000000 /* clear */ 399 400#ifndef CONFIG_PRELOADER 401clbss_l:str r2, [r0] /* clear loop... */ 402 add r0, r0, #4 403 cmp r0, r1 404 bne clbss_l 405#endif 406 407 ldr r0, _start_armboot_ofs 408 adr r1, _start 409 add r0, r0, r1 410 ldr pc, r0 411 412_start_armboot_ofs: 413#ifdef CONFIG_NAND_SPL 414 .word nand_boot - _start 415#else 416#ifdef CONFIG_ONENAND_IPL 417 .word start_oneboot - _start 418#else 419 .word start_armboot - _start 420#endif /* CONFIG_ONENAND_IPL */ 421#endif /* CONFIG_NAND_SPL */ 422 423#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ 424 425/* 426 ************************************************************************* 427 * 428 * CPU_init_critical registers 429 * 430 * setup important registers 431 * setup memory timing 432 * 433 ************************************************************************* 434 */ 435#ifndef CONFIG_SKIP_LOWLEVEL_INIT 436cpu_init_crit: 437 /* 438 * flush v4 I/D caches 439 */ 440 mov r0, #0 441 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 442 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 443 444 /* 445 * disable MMU stuff and caches 446 */ 447 mrc p15, 0, r0, c1, c0, 0 448 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 449 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 450 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 451 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 452 mcr p15, 0, r0, c1, c0, 0 453 454 /* 455 * Jump to board specific initialization... The Mask ROM will have already initialized 456 * basic memory. Go here to bump up clock rate and handle wake up conditions. 457 */ 458 mov ip, lr /* persevere link reg across call */ 459 bl lowlevel_init /* go setup pll,mux,memory */ 460 mov lr, ip /* restore link */ 461 mov pc, lr /* back to my caller */ 462#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 463 464#ifndef CONFIG_PRELOADER 465/* 466 ************************************************************************* 467 * 468 * Interrupt handling 469 * 470 ************************************************************************* 471 */ 472@ 473@ IRQ stack frame. 474@ 475#define S_FRAME_SIZE 72 476 477#define S_OLD_R0 68 478#define S_PSR 64 479#define S_PC 60 480#define S_LR 56 481#define S_SP 52 482 483#define S_IP 48 484#define S_FP 44 485#define S_R10 40 486#define S_R9 36 487#define S_R8 32 488#define S_R7 28 489#define S_R6 24 490#define S_R5 20 491#define S_R4 16 492#define S_R3 12 493#define S_R2 8 494#define S_R1 4 495#define S_R0 0 496 497#define MODE_SVC 0x13 498#define I_BIT 0x80 499 500/* 501 * use bad_save_user_regs for abort/prefetch/undef/swi ... 502 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 503 */ 504 505 .macro bad_save_user_regs 506 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 507 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 508 509#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 510 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 511#else 512 adr r2, _start 513 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) 514 sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8) @ set base 2 words into abort stack 515#endif 516 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 517 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 518 519 add r5, sp, #S_SP 520 mov r1, lr 521 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 522 mov r0, sp @ save current stack into r0 (param register) 523 .endm 524 525 .macro irq_save_user_regs 526 sub sp, sp, #S_FRAME_SIZE 527 stmia sp, {r0 - r12} @ Calling r0-r12 528 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 529 stmdb r8, {sp, lr}^ @ Calling SP, LR 530 str lr, [r8, #0] @ Save calling PC 531 mrs r6, spsr 532 str r6, [r8, #4] @ Save CPSR 533 str r0, [r8, #8] @ Save OLD_R0 534 mov r0, sp 535 .endm 536 537 .macro irq_restore_user_regs 538 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 539 mov r0, r0 540 ldr lr, [sp, #S_PC] @ Get PC 541 add sp, sp, #S_FRAME_SIZE 542 subs pc, lr, #4 @ return & move spsr_svc into cpsr 543 .endm 544 545 .macro get_bad_stack 546#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 547 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 548#else 549 adr r13, _start @ setup our mode stack (enter in banked mode) 550 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) @ move past malloc pool 551 sub r13, r13, #(GENERATED_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack 552#endif 553 554 str lr, [r13] @ save caller lr in position 0 of saved stack 555 mrs lr, spsr @ get the spsr 556 str lr, [r13, #4] @ save spsr in position 1 of saved stack 557 558 mov r13, #MODE_SVC @ prepare SVC-Mode 559 @ msr spsr_c, r13 560 msr spsr, r13 @ switch modes, make sure moves will execute 561 mov lr, pc @ capture return pc 562 movs pc, lr @ jump to next instruction & switch modes. 563 .endm 564 565 .macro get_bad_stack_swi 566 sub r13, r13, #4 @ space on current stack for scratch reg. 567 str r0, [r13] @ save R0's value. 568#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 569 ldr r0, IRQ_STACK_START_IN @ get data regions start 570#else 571 ldr r0, _armboot_start @ get data regions start 572 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool 573 sub r0, r0, #(GENERATED_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack 574#endif 575 str lr, [r0] @ save caller lr in position 0 of saved stack 576 mrs r0, spsr @ get the spsr 577 str lr, [r0, #4] @ save spsr in position 1 of saved stack 578 ldr r0, [r13] @ restore r0 579 add r13, r13, #4 @ pop stack entry 580 .endm 581 582 .macro get_irq_stack @ setup IRQ stack 583 ldr sp, IRQ_STACK_START 584 .endm 585 586 .macro get_fiq_stack @ setup FIQ stack 587 ldr sp, FIQ_STACK_START 588 .endm 589#endif /* CONFIG_PRELOADER */ 590 591/* 592 * exception handlers 593 */ 594#ifdef CONFIG_PRELOADER 595 .align 5 596do_hang: 597 ldr sp, _TEXT_BASE /* use 32 words about stack */ 598 bl hang /* hang and never return */ 599#else /* !CONFIG_PRELOADER */ 600 .align 5 601undefined_instruction: 602 get_bad_stack 603 bad_save_user_regs 604 bl do_undefined_instruction 605 606 .align 5 607software_interrupt: 608 get_bad_stack_swi 609 bad_save_user_regs 610 bl do_software_interrupt 611 612 .align 5 613prefetch_abort: 614 get_bad_stack 615 bad_save_user_regs 616 bl do_prefetch_abort 617 618 .align 5 619data_abort: 620 get_bad_stack 621 bad_save_user_regs 622 bl do_data_abort 623 624 .align 5 625not_used: 626 get_bad_stack 627 bad_save_user_regs 628 bl do_not_used 629 630#ifdef CONFIG_USE_IRQ 631 632 .align 5 633irq: 634 get_irq_stack 635 irq_save_user_regs 636 bl do_irq 637 irq_restore_user_regs 638 639 .align 5 640fiq: 641 get_fiq_stack 642 /* someone ought to write a more effiction fiq_save_user_regs */ 643 irq_save_user_regs 644 bl do_fiq 645 irq_restore_user_regs 646 647#else 648 649 .align 5 650irq: 651 get_bad_stack 652 bad_save_user_regs 653 bl do_irq 654 655 .align 5 656fiq: 657 get_bad_stack 658 bad_save_user_regs 659 bl do_fiq 660 661#endif 662 .align 5 663.global arm1136_cache_flush 664arm1136_cache_flush: 665#if !defined(CONFIG_SYS_NO_ICACHE) 666 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 667#endif 668#if !defined(CONFIG_SYS_NO_DCACHE) 669 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 670#endif 671 mov pc, lr @ back to caller 672#endif /* CONFIG_PRELOADER */ 673