1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15#include <asm-offsets.h> 16#include <config.h> 17 18/* 19 ************************************************************************* 20 * 21 * Startup Code (reset vector) 22 * 23 * do important init only if we don't start from memory! 24 * setup Memory and board specific bits prior to relocation. 25 * relocate armboot to ram 26 * setup stack 27 * 28 ************************************************************************* 29 */ 30 31 .globl reset 32 33reset: 34 /* 35 * set the cpu to SVC32 mode 36 */ 37 mrs r0,cpsr 38 bic r0,r0,#0x1f 39 orr r0,r0,#0xd3 40 msr cpsr,r0 41 42 /* the mask ROM code should have PLL and others stable */ 43#ifndef CONFIG_SKIP_LOWLEVEL_INIT 44 bl cpu_init_crit 45#endif 46 47 bl _main 48 49/*------------------------------------------------------------------------------*/ 50 51 .globl c_runtime_cpu_setup 52c_runtime_cpu_setup: 53 54 bx lr 55 56/* 57 ************************************************************************* 58 * 59 * CPU_init_critical registers 60 * 61 * setup important registers 62 * setup memory timing 63 * 64 ************************************************************************* 65 */ 66#ifndef CONFIG_SKIP_LOWLEVEL_INIT 67cpu_init_crit: 68 /* 69 * flush v4 I/D caches 70 */ 71 mov r0, #0 72 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 73 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 74 75 /* 76 * disable MMU stuff and caches 77 */ 78 mrc p15, 0, r0, c1, c0, 0 79 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 80 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 81 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 82 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 83 mcr p15, 0, r0, c1, c0, 0 84 85 /* 86 * Jump to board specific initialization... The Mask ROM will have already initialized 87 * basic memory. Go here to bump up clock rate and handle wake up conditions. 88 */ 89 mov ip, lr /* persevere link reg across call */ 90 bl lowlevel_init /* go setup pll,mux,memory */ 91 mov lr, ip /* restore link */ 92 mov pc, lr /* back to my caller */ 93#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 94