1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word __bss_end__ - _start 106 107.globl _end_ofs 108_end_ofs: 109 .word _end - _start 110 111#ifdef CONFIG_USE_IRQ 112/* IRQ stack memory (calculated at run-time) */ 113.globl IRQ_STACK_START 114IRQ_STACK_START: 115 .word 0x0badc0de 116 117/* IRQ stack memory (calculated at run-time) */ 118.globl FIQ_STACK_START 119FIQ_STACK_START: 120 .word 0x0badc0de 121#endif 122 123/* IRQ stack memory (calculated at run-time) + 8 bytes */ 124.globl IRQ_STACK_START_IN 125IRQ_STACK_START_IN: 126 .word 0x0badc0de 127 128/* 129 * the actual reset code 130 */ 131 132reset: 133 /* 134 * set the cpu to SVC32 mode 135 */ 136 mrs r0,cpsr 137 bic r0,r0,#0x1f 138 orr r0,r0,#0xd3 139 msr cpsr,r0 140 141#ifdef CONFIG_OMAP2420H4 142 /* Copy vectors to mask ROM indirect addr */ 143 adr r0, _start /* r0 <- current position of code */ 144 add r0, r0, #4 /* skip reset vector */ 145 mov r2, #64 /* r2 <- size to copy */ 146 add r2, r0, r2 /* r2 <- source end address */ 147 mov r1, #SRAM_OFFSET0 /* build vect addr */ 148 mov r3, #SRAM_OFFSET1 149 add r1, r1, r3 150 mov r3, #SRAM_OFFSET2 151 add r1, r1, r3 152next: 153 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 154 stmia r1!, {r3-r10} /* copy to target address [r1] */ 155 cmp r0, r2 /* until source end address [r2] */ 156 bne next /* loop until equal */ 157 bl cpy_clk_code /* put dpll adjust code behind vectors */ 158#endif 159 /* the mask ROM code should have PLL and others stable */ 160#ifndef CONFIG_SKIP_LOWLEVEL_INIT 161 bl cpu_init_crit 162#endif 163 164/* Set stackpointer in internal RAM to call board_init_f */ 165call_board_init_f: 166 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 167 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 168 ldr r0,=0x00000000 169 170 bl board_init_f 171 172/*------------------------------------------------------------------------------*/ 173 174/* 175 * void relocate_code (addr_sp, gd, addr_moni) 176 * 177 * This "function" does not return, instead it continues in RAM 178 * after relocating the monitor code. 179 * 180 */ 181 .globl relocate_code 182relocate_code: 183 mov r4, r0 /* save addr_sp */ 184 mov r5, r1 /* save addr of gd */ 185 mov r6, r2 /* save addr of destination */ 186 187 /* Set up the stack */ 188stack_setup: 189 mov sp, r4 190 191 adr r0, _start 192 cmp r0, r6 193 beq clear_bss /* skip relocation */ 194 mov r1, r6 /* r1 <- scratch for copy_loop */ 195 ldr r3, _bss_start_ofs 196 add r2, r0, r3 /* r2 <- source end address */ 197 198copy_loop: 199 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 200 stmia r1!, {r9-r10} /* copy to target address [r1] */ 201 cmp r0, r2 /* until source end address [r2] */ 202 blo copy_loop 203 204#ifndef CONFIG_SPL_BUILD 205 /* 206 * fix .rel.dyn relocations 207 */ 208 ldr r0, _TEXT_BASE /* r0 <- Text base */ 209 sub r9, r6, r0 /* r9 <- relocation offset */ 210 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 211 add r10, r10, r0 /* r10 <- sym table in FLASH */ 212 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 213 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 214 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 215 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 216fixloop: 217 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 218 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 219 ldr r1, [r2, #4] 220 and r7, r1, #0xff 221 cmp r7, #23 /* relative fixup? */ 222 beq fixrel 223 cmp r7, #2 /* absolute fixup? */ 224 beq fixabs 225 /* ignore unknown type of fixup */ 226 b fixnext 227fixabs: 228 /* absolute fix: set location to (offset) symbol value */ 229 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 230 add r1, r10, r1 /* r1 <- address of symbol in table */ 231 ldr r1, [r1, #4] /* r1 <- symbol value */ 232 add r1, r1, r9 /* r1 <- relocated sym addr */ 233 b fixnext 234fixrel: 235 /* relative fix: increase location by offset */ 236 ldr r1, [r0] 237 add r1, r1, r9 238fixnext: 239 str r1, [r0] 240 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 241 cmp r2, r3 242 blo fixloop 243#endif 244 245clear_bss: 246#ifndef CONFIG_SPL_BUILD 247 ldr r0, _bss_start_ofs 248 ldr r1, _bss_end_ofs 249 mov r4, r6 /* reloc addr */ 250 add r0, r0, r4 251 add r1, r1, r4 252 mov r2, #0x00000000 /* clear */ 253 254clbss_l:str r2, [r0] /* clear loop... */ 255 add r0, r0, #4 256 cmp r0, r1 257 bne clbss_l 258#endif /* #ifndef CONFIG_SPL_BUILD */ 259 260/* 261 * We are done. Do not return, instead branch to second part of board 262 * initialization, now running from RAM. 263 */ 264#ifdef CONFIG_NAND_SPL 265 ldr r0, _nand_boot_ofs 266 mov pc, r0 267 268_nand_boot_ofs: 269 .word nand_boot 270#else 271jump_2_ram: 272 ldr r0, _board_init_r_ofs 273 ldr r1, _TEXT_BASE 274 add lr, r0, r1 275 add lr, lr, r9 276 /* setup parameters for board_init_r */ 277 mov r0, r5 /* gd_t */ 278 mov r1, r6 /* dest_addr */ 279 /* jump to it ... */ 280 mov pc, lr 281 282_board_init_r_ofs: 283 .word board_init_r - _start 284#endif 285 286_rel_dyn_start_ofs: 287 .word __rel_dyn_start - _start 288_rel_dyn_end_ofs: 289 .word __rel_dyn_end - _start 290_dynsym_start_ofs: 291 .word __dynsym_start - _start 292 293/* 294 ************************************************************************* 295 * 296 * CPU_init_critical registers 297 * 298 * setup important registers 299 * setup memory timing 300 * 301 ************************************************************************* 302 */ 303#ifndef CONFIG_SKIP_LOWLEVEL_INIT 304cpu_init_crit: 305 /* 306 * flush v4 I/D caches 307 */ 308 mov r0, #0 309 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 310 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 311 312 /* 313 * disable MMU stuff and caches 314 */ 315 mrc p15, 0, r0, c1, c0, 0 316 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 317 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 318 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 319 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 320 mcr p15, 0, r0, c1, c0, 0 321 322 /* 323 * Jump to board specific initialization... The Mask ROM will have already initialized 324 * basic memory. Go here to bump up clock rate and handle wake up conditions. 325 */ 326 mov ip, lr /* persevere link reg across call */ 327 bl lowlevel_init /* go setup pll,mux,memory */ 328 mov lr, ip /* restore link */ 329 mov pc, lr /* back to my caller */ 330#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 331 332#ifndef CONFIG_SPL_BUILD 333/* 334 ************************************************************************* 335 * 336 * Interrupt handling 337 * 338 ************************************************************************* 339 */ 340@ 341@ IRQ stack frame. 342@ 343#define S_FRAME_SIZE 72 344 345#define S_OLD_R0 68 346#define S_PSR 64 347#define S_PC 60 348#define S_LR 56 349#define S_SP 52 350 351#define S_IP 48 352#define S_FP 44 353#define S_R10 40 354#define S_R9 36 355#define S_R8 32 356#define S_R7 28 357#define S_R6 24 358#define S_R5 20 359#define S_R4 16 360#define S_R3 12 361#define S_R2 8 362#define S_R1 4 363#define S_R0 0 364 365#define MODE_SVC 0x13 366#define I_BIT 0x80 367 368/* 369 * use bad_save_user_regs for abort/prefetch/undef/swi ... 370 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 371 */ 372 373 .macro bad_save_user_regs 374 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 375 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 376 377 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 378 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 379 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 380 381 add r5, sp, #S_SP 382 mov r1, lr 383 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 384 mov r0, sp @ save current stack into r0 (param register) 385 .endm 386 387 .macro irq_save_user_regs 388 sub sp, sp, #S_FRAME_SIZE 389 stmia sp, {r0 - r12} @ Calling r0-r12 390 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 391 stmdb r8, {sp, lr}^ @ Calling SP, LR 392 str lr, [r8, #0] @ Save calling PC 393 mrs r6, spsr 394 str r6, [r8, #4] @ Save CPSR 395 str r0, [r8, #8] @ Save OLD_R0 396 mov r0, sp 397 .endm 398 399 .macro irq_restore_user_regs 400 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 401 mov r0, r0 402 ldr lr, [sp, #S_PC] @ Get PC 403 add sp, sp, #S_FRAME_SIZE 404 subs pc, lr, #4 @ return & move spsr_svc into cpsr 405 .endm 406 407 .macro get_bad_stack 408 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 409 410 str lr, [r13] @ save caller lr in position 0 of saved stack 411 mrs lr, spsr @ get the spsr 412 str lr, [r13, #4] @ save spsr in position 1 of saved stack 413 414 mov r13, #MODE_SVC @ prepare SVC-Mode 415 @ msr spsr_c, r13 416 msr spsr, r13 @ switch modes, make sure moves will execute 417 mov lr, pc @ capture return pc 418 movs pc, lr @ jump to next instruction & switch modes. 419 .endm 420 421 .macro get_bad_stack_swi 422 sub r13, r13, #4 @ space on current stack for scratch reg. 423 str r0, [r13] @ save R0's value. 424 ldr r0, IRQ_STACK_START_IN @ get data regions start 425 str lr, [r0] @ save caller lr in position 0 of saved stack 426 mrs r0, spsr @ get the spsr 427 str lr, [r0, #4] @ save spsr in position 1 of saved stack 428 ldr r0, [r13] @ restore r0 429 add r13, r13, #4 @ pop stack entry 430 .endm 431 432 .macro get_irq_stack @ setup IRQ stack 433 ldr sp, IRQ_STACK_START 434 .endm 435 436 .macro get_fiq_stack @ setup FIQ stack 437 ldr sp, FIQ_STACK_START 438 .endm 439#endif /* CONFIG_SPL_BUILD */ 440 441/* 442 * exception handlers 443 */ 444#ifdef CONFIG_SPL_BUILD 445 .align 5 446do_hang: 447 ldr sp, _TEXT_BASE /* use 32 words about stack */ 448 bl hang /* hang and never return */ 449#else /* !CONFIG_SPL_BUILD */ 450 .align 5 451undefined_instruction: 452 get_bad_stack 453 bad_save_user_regs 454 bl do_undefined_instruction 455 456 .align 5 457software_interrupt: 458 get_bad_stack_swi 459 bad_save_user_regs 460 bl do_software_interrupt 461 462 .align 5 463prefetch_abort: 464 get_bad_stack 465 bad_save_user_regs 466 bl do_prefetch_abort 467 468 .align 5 469data_abort: 470 get_bad_stack 471 bad_save_user_regs 472 bl do_data_abort 473 474 .align 5 475not_used: 476 get_bad_stack 477 bad_save_user_regs 478 bl do_not_used 479 480#ifdef CONFIG_USE_IRQ 481 482 .align 5 483irq: 484 get_irq_stack 485 irq_save_user_regs 486 bl do_irq 487 irq_restore_user_regs 488 489 .align 5 490fiq: 491 get_fiq_stack 492 /* someone ought to write a more effiction fiq_save_user_regs */ 493 irq_save_user_regs 494 bl do_fiq 495 irq_restore_user_regs 496 497#else 498 499 .align 5 500irq: 501 get_bad_stack 502 bad_save_user_regs 503 bl do_irq 504 505 .align 5 506fiq: 507 get_bad_stack 508 bad_save_user_regs 509 bl do_fiq 510 511#endif 512 .align 5 513.global arm1136_cache_flush 514arm1136_cache_flush: 515#if !defined(CONFIG_SYS_ICACHE_OFF) 516 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 517#endif 518#if !defined(CONFIG_SYS_DCACHE_OFF) 519 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 520#endif 521 mov pc, lr @ back to caller 522#endif /* CONFIG_SPL_BUILD */ 523