1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 92 .word CONFIG_SPL_TEXT_BASE 93#else 94 .word CONFIG_SYS_TEXT_BASE 95#endif 96 97/* 98 * These are defined in the board-specific linker script. 99 * Subtracting _start from them lets the linker put their 100 * relative position in the executable instead of leaving 101 * them null. 102 */ 103.globl _bss_start_ofs 104_bss_start_ofs: 105 .word __bss_start - _start 106 107.globl _bss_end_ofs 108_bss_end_ofs: 109 .word __bss_end - _start 110 111.globl _end_ofs 112_end_ofs: 113 .word _end - _start 114 115#ifdef CONFIG_USE_IRQ 116/* IRQ stack memory (calculated at run-time) */ 117.globl IRQ_STACK_START 118IRQ_STACK_START: 119 .word 0x0badc0de 120 121/* IRQ stack memory (calculated at run-time) */ 122.globl FIQ_STACK_START 123FIQ_STACK_START: 124 .word 0x0badc0de 125#endif 126 127/* IRQ stack memory (calculated at run-time) + 8 bytes */ 128.globl IRQ_STACK_START_IN 129IRQ_STACK_START_IN: 130 .word 0x0badc0de 131 132/* 133 * the actual reset code 134 */ 135 136reset: 137 /* 138 * set the cpu to SVC32 mode 139 */ 140 mrs r0,cpsr 141 bic r0,r0,#0x1f 142 orr r0,r0,#0xd3 143 msr cpsr,r0 144 145 /* the mask ROM code should have PLL and others stable */ 146#ifndef CONFIG_SKIP_LOWLEVEL_INIT 147 bl cpu_init_crit 148#endif 149 150 bl _main 151 152/*------------------------------------------------------------------------------*/ 153 154 .globl c_runtime_cpu_setup 155c_runtime_cpu_setup: 156 157 bx lr 158 159/* 160 ************************************************************************* 161 * 162 * CPU_init_critical registers 163 * 164 * setup important registers 165 * setup memory timing 166 * 167 ************************************************************************* 168 */ 169#ifndef CONFIG_SKIP_LOWLEVEL_INIT 170cpu_init_crit: 171 /* 172 * flush v4 I/D caches 173 */ 174 mov r0, #0 175 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 176 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 177 178 /* 179 * disable MMU stuff and caches 180 */ 181 mrc p15, 0, r0, c1, c0, 0 182 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 183 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 184 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 185 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 186 mcr p15, 0, r0, c1, c0, 0 187 188 /* 189 * Jump to board specific initialization... The Mask ROM will have already initialized 190 * basic memory. Go here to bump up clock rate and handle wake up conditions. 191 */ 192 mov ip, lr /* persevere link reg across call */ 193 bl lowlevel_init /* go setup pll,mux,memory */ 194 mov lr, ip /* restore link */ 195 mov pc, lr /* back to my caller */ 196#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 197 198#ifndef CONFIG_SPL_BUILD 199/* 200 ************************************************************************* 201 * 202 * Interrupt handling 203 * 204 ************************************************************************* 205 */ 206@ 207@ IRQ stack frame. 208@ 209#define S_FRAME_SIZE 72 210 211#define S_OLD_R0 68 212#define S_PSR 64 213#define S_PC 60 214#define S_LR 56 215#define S_SP 52 216 217#define S_IP 48 218#define S_FP 44 219#define S_R10 40 220#define S_R9 36 221#define S_R8 32 222#define S_R7 28 223#define S_R6 24 224#define S_R5 20 225#define S_R4 16 226#define S_R3 12 227#define S_R2 8 228#define S_R1 4 229#define S_R0 0 230 231#define MODE_SVC 0x13 232#define I_BIT 0x80 233 234/* 235 * use bad_save_user_regs for abort/prefetch/undef/swi ... 236 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 237 */ 238 239 .macro bad_save_user_regs 240 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 241 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 242 243 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 244 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 245 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 246 247 add r5, sp, #S_SP 248 mov r1, lr 249 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 250 mov r0, sp @ save current stack into r0 (param register) 251 .endm 252 253 .macro irq_save_user_regs 254 sub sp, sp, #S_FRAME_SIZE 255 stmia sp, {r0 - r12} @ Calling r0-r12 256 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 257 stmdb r8, {sp, lr}^ @ Calling SP, LR 258 str lr, [r8, #0] @ Save calling PC 259 mrs r6, spsr 260 str r6, [r8, #4] @ Save CPSR 261 str r0, [r8, #8] @ Save OLD_R0 262 mov r0, sp 263 .endm 264 265 .macro irq_restore_user_regs 266 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 267 mov r0, r0 268 ldr lr, [sp, #S_PC] @ Get PC 269 add sp, sp, #S_FRAME_SIZE 270 subs pc, lr, #4 @ return & move spsr_svc into cpsr 271 .endm 272 273 .macro get_bad_stack 274 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 275 276 str lr, [r13] @ save caller lr in position 0 of saved stack 277 mrs lr, spsr @ get the spsr 278 str lr, [r13, #4] @ save spsr in position 1 of saved stack 279 280 mov r13, #MODE_SVC @ prepare SVC-Mode 281 @ msr spsr_c, r13 282 msr spsr, r13 @ switch modes, make sure moves will execute 283 mov lr, pc @ capture return pc 284 movs pc, lr @ jump to next instruction & switch modes. 285 .endm 286 287 .macro get_bad_stack_swi 288 sub r13, r13, #4 @ space on current stack for scratch reg. 289 str r0, [r13] @ save R0's value. 290 ldr r0, IRQ_STACK_START_IN @ get data regions start 291 str lr, [r0] @ save caller lr in position 0 of saved stack 292 mrs lr, spsr @ get the spsr 293 str lr, [r0, #4] @ save spsr in position 1 of saved stack 294 ldr lr, [r0] @ restore lr 295 ldr r0, [r13] @ restore r0 296 add r13, r13, #4 @ pop stack entry 297 .endm 298 299 .macro get_irq_stack @ setup IRQ stack 300 ldr sp, IRQ_STACK_START 301 .endm 302 303 .macro get_fiq_stack @ setup FIQ stack 304 ldr sp, FIQ_STACK_START 305 .endm 306#endif /* CONFIG_SPL_BUILD */ 307 308/* 309 * exception handlers 310 */ 311#ifdef CONFIG_SPL_BUILD 312 .align 5 313do_hang: 314 ldr sp, _TEXT_BASE /* use 32 words about stack */ 315 bl hang /* hang and never return */ 316#else /* !CONFIG_SPL_BUILD */ 317 .align 5 318undefined_instruction: 319 get_bad_stack 320 bad_save_user_regs 321 bl do_undefined_instruction 322 323 .align 5 324software_interrupt: 325 get_bad_stack_swi 326 bad_save_user_regs 327 bl do_software_interrupt 328 329 .align 5 330prefetch_abort: 331 get_bad_stack 332 bad_save_user_regs 333 bl do_prefetch_abort 334 335 .align 5 336data_abort: 337 get_bad_stack 338 bad_save_user_regs 339 bl do_data_abort 340 341 .align 5 342not_used: 343 get_bad_stack 344 bad_save_user_regs 345 bl do_not_used 346 347#ifdef CONFIG_USE_IRQ 348 349 .align 5 350irq: 351 get_irq_stack 352 irq_save_user_regs 353 bl do_irq 354 irq_restore_user_regs 355 356 .align 5 357fiq: 358 get_fiq_stack 359 /* someone ought to write a more effiction fiq_save_user_regs */ 360 irq_save_user_regs 361 bl do_fiq 362 irq_restore_user_regs 363 364#else 365 366 .align 5 367irq: 368 get_bad_stack 369 bad_save_user_regs 370 bl do_irq 371 372 .align 5 373fiq: 374 get_bad_stack 375 bad_save_user_regs 376 bl do_fiq 377 378#endif 379 .align 5 380.global arm1136_cache_flush 381arm1136_cache_flush: 382#if !defined(CONFIG_SYS_ICACHE_OFF) 383 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 384#endif 385#if !defined(CONFIG_SYS_DCACHE_OFF) 386 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 387#endif 388 mov pc, lr @ back to caller 389#endif /* CONFIG_SPL_BUILD */ 390