1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word __bss_end__ - _start 106 107.globl _end_ofs 108_end_ofs: 109 .word _end - _start 110 111#ifdef CONFIG_USE_IRQ 112/* IRQ stack memory (calculated at run-time) */ 113.globl IRQ_STACK_START 114IRQ_STACK_START: 115 .word 0x0badc0de 116 117/* IRQ stack memory (calculated at run-time) */ 118.globl FIQ_STACK_START 119FIQ_STACK_START: 120 .word 0x0badc0de 121#endif 122 123/* IRQ stack memory (calculated at run-time) + 8 bytes */ 124.globl IRQ_STACK_START_IN 125IRQ_STACK_START_IN: 126 .word 0x0badc0de 127 128/* 129 * the actual reset code 130 */ 131 132reset: 133 /* 134 * set the cpu to SVC32 mode 135 */ 136 mrs r0,cpsr 137 bic r0,r0,#0x1f 138 orr r0,r0,#0xd3 139 msr cpsr,r0 140 141#ifdef CONFIG_OMAP2420H4 142 /* Copy vectors to mask ROM indirect addr */ 143 adr r0, _start /* r0 <- current position of code */ 144 add r0, r0, #4 /* skip reset vector */ 145 mov r2, #64 /* r2 <- size to copy */ 146 add r2, r0, r2 /* r2 <- source end address */ 147 mov r1, #SRAM_OFFSET0 /* build vect addr */ 148 mov r3, #SRAM_OFFSET1 149 add r1, r1, r3 150 mov r3, #SRAM_OFFSET2 151 add r1, r1, r3 152next: 153 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 154 stmia r1!, {r3-r10} /* copy to target address [r1] */ 155 cmp r0, r2 /* until source end address [r2] */ 156 bne next /* loop until equal */ 157 bl cpy_clk_code /* put dpll adjust code behind vectors */ 158#endif 159 /* the mask ROM code should have PLL and others stable */ 160#ifndef CONFIG_SKIP_LOWLEVEL_INIT 161 bl cpu_init_crit 162#endif 163 164/* Set stackpointer in internal RAM to call board_init_f */ 165call_board_init_f: 166 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 167 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 168 ldr r0,=0x00000000 169 170 bl board_init_f 171 172/*------------------------------------------------------------------------------*/ 173 174/* 175 * void relocate_code (addr_sp, gd, addr_moni) 176 * 177 * This "function" does not return, instead it continues in RAM 178 * after relocating the monitor code. 179 * 180 */ 181 .globl relocate_code 182relocate_code: 183 mov r4, r0 /* save addr_sp */ 184 mov r5, r1 /* save addr of gd */ 185 mov r6, r2 /* save addr of destination */ 186 187 /* Set up the stack */ 188stack_setup: 189 mov sp, r4 190 191 adr r0, _start 192 cmp r0, r6 193 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 194 beq clear_bss /* skip relocation */ 195 mov r1, r6 /* r1 <- scratch for copy_loop */ 196 ldr r3, _bss_start_ofs 197 add r2, r0, r3 /* r2 <- source end address */ 198 199copy_loop: 200 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 201 stmia r1!, {r9-r10} /* copy to target address [r1] */ 202 cmp r0, r2 /* until source end address [r2] */ 203 blo copy_loop 204 205#ifndef CONFIG_SPL_BUILD 206 /* 207 * fix .rel.dyn relocations 208 */ 209 ldr r0, _TEXT_BASE /* r0 <- Text base */ 210 sub r9, r6, r0 /* r9 <- relocation offset */ 211 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 212 add r10, r10, r0 /* r10 <- sym table in FLASH */ 213 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 214 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 215 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 216 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 217fixloop: 218 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 219 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 220 ldr r1, [r2, #4] 221 and r7, r1, #0xff 222 cmp r7, #23 /* relative fixup? */ 223 beq fixrel 224 cmp r7, #2 /* absolute fixup? */ 225 beq fixabs 226 /* ignore unknown type of fixup */ 227 b fixnext 228fixabs: 229 /* absolute fix: set location to (offset) symbol value */ 230 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 231 add r1, r10, r1 /* r1 <- address of symbol in table */ 232 ldr r1, [r1, #4] /* r1 <- symbol value */ 233 add r1, r1, r9 /* r1 <- relocated sym addr */ 234 b fixnext 235fixrel: 236 /* relative fix: increase location by offset */ 237 ldr r1, [r0] 238 add r1, r1, r9 239fixnext: 240 str r1, [r0] 241 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 242 cmp r2, r3 243 blo fixloop 244#endif 245 246clear_bss: 247#ifndef CONFIG_SPL_BUILD 248 ldr r0, _bss_start_ofs 249 ldr r1, _bss_end_ofs 250 mov r4, r6 /* reloc addr */ 251 add r0, r0, r4 252 add r1, r1, r4 253 mov r2, #0x00000000 /* clear */ 254 255clbss_l:cmp r0, r1 /* clear loop... */ 256 bhs clbss_e /* if reached end of bss, exit */ 257 str r2, [r0] 258 add r0, r0, #4 259 b clbss_l 260clbss_e: 261#endif /* #ifndef CONFIG_SPL_BUILD */ 262 263/* 264 * We are done. Do not return, instead branch to second part of board 265 * initialization, now running from RAM. 266 */ 267#ifdef CONFIG_NAND_SPL 268 ldr r0, _nand_boot_ofs 269 mov pc, r0 270 271_nand_boot_ofs: 272 .word nand_boot 273#else 274jump_2_ram: 275 ldr r0, _board_init_r_ofs 276 ldr r1, _TEXT_BASE 277 add lr, r0, r1 278 add lr, lr, r9 279 /* setup parameters for board_init_r */ 280 mov r0, r5 /* gd_t */ 281 mov r1, r6 /* dest_addr */ 282 /* jump to it ... */ 283 mov pc, lr 284 285_board_init_r_ofs: 286 .word board_init_r - _start 287#endif 288 289_rel_dyn_start_ofs: 290 .word __rel_dyn_start - _start 291_rel_dyn_end_ofs: 292 .word __rel_dyn_end - _start 293_dynsym_start_ofs: 294 .word __dynsym_start - _start 295 296/* 297 ************************************************************************* 298 * 299 * CPU_init_critical registers 300 * 301 * setup important registers 302 * setup memory timing 303 * 304 ************************************************************************* 305 */ 306#ifndef CONFIG_SKIP_LOWLEVEL_INIT 307cpu_init_crit: 308 /* 309 * flush v4 I/D caches 310 */ 311 mov r0, #0 312 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 313 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 314 315 /* 316 * disable MMU stuff and caches 317 */ 318 mrc p15, 0, r0, c1, c0, 0 319 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 320 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 321 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 322 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 323 mcr p15, 0, r0, c1, c0, 0 324 325 /* 326 * Jump to board specific initialization... The Mask ROM will have already initialized 327 * basic memory. Go here to bump up clock rate and handle wake up conditions. 328 */ 329 mov ip, lr /* persevere link reg across call */ 330 bl lowlevel_init /* go setup pll,mux,memory */ 331 mov lr, ip /* restore link */ 332 mov pc, lr /* back to my caller */ 333#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 334 335#ifndef CONFIG_SPL_BUILD 336/* 337 ************************************************************************* 338 * 339 * Interrupt handling 340 * 341 ************************************************************************* 342 */ 343@ 344@ IRQ stack frame. 345@ 346#define S_FRAME_SIZE 72 347 348#define S_OLD_R0 68 349#define S_PSR 64 350#define S_PC 60 351#define S_LR 56 352#define S_SP 52 353 354#define S_IP 48 355#define S_FP 44 356#define S_R10 40 357#define S_R9 36 358#define S_R8 32 359#define S_R7 28 360#define S_R6 24 361#define S_R5 20 362#define S_R4 16 363#define S_R3 12 364#define S_R2 8 365#define S_R1 4 366#define S_R0 0 367 368#define MODE_SVC 0x13 369#define I_BIT 0x80 370 371/* 372 * use bad_save_user_regs for abort/prefetch/undef/swi ... 373 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 374 */ 375 376 .macro bad_save_user_regs 377 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 378 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 379 380 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 381 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 382 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 383 384 add r5, sp, #S_SP 385 mov r1, lr 386 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 387 mov r0, sp @ save current stack into r0 (param register) 388 .endm 389 390 .macro irq_save_user_regs 391 sub sp, sp, #S_FRAME_SIZE 392 stmia sp, {r0 - r12} @ Calling r0-r12 393 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 394 stmdb r8, {sp, lr}^ @ Calling SP, LR 395 str lr, [r8, #0] @ Save calling PC 396 mrs r6, spsr 397 str r6, [r8, #4] @ Save CPSR 398 str r0, [r8, #8] @ Save OLD_R0 399 mov r0, sp 400 .endm 401 402 .macro irq_restore_user_regs 403 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 404 mov r0, r0 405 ldr lr, [sp, #S_PC] @ Get PC 406 add sp, sp, #S_FRAME_SIZE 407 subs pc, lr, #4 @ return & move spsr_svc into cpsr 408 .endm 409 410 .macro get_bad_stack 411 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 412 413 str lr, [r13] @ save caller lr in position 0 of saved stack 414 mrs lr, spsr @ get the spsr 415 str lr, [r13, #4] @ save spsr in position 1 of saved stack 416 417 mov r13, #MODE_SVC @ prepare SVC-Mode 418 @ msr spsr_c, r13 419 msr spsr, r13 @ switch modes, make sure moves will execute 420 mov lr, pc @ capture return pc 421 movs pc, lr @ jump to next instruction & switch modes. 422 .endm 423 424 .macro get_bad_stack_swi 425 sub r13, r13, #4 @ space on current stack for scratch reg. 426 str r0, [r13] @ save R0's value. 427 ldr r0, IRQ_STACK_START_IN @ get data regions start 428 str lr, [r0] @ save caller lr in position 0 of saved stack 429 mrs r0, spsr @ get the spsr 430 str lr, [r0, #4] @ save spsr in position 1 of saved stack 431 ldr r0, [r13] @ restore r0 432 add r13, r13, #4 @ pop stack entry 433 .endm 434 435 .macro get_irq_stack @ setup IRQ stack 436 ldr sp, IRQ_STACK_START 437 .endm 438 439 .macro get_fiq_stack @ setup FIQ stack 440 ldr sp, FIQ_STACK_START 441 .endm 442#endif /* CONFIG_SPL_BUILD */ 443 444/* 445 * exception handlers 446 */ 447#ifdef CONFIG_SPL_BUILD 448 .align 5 449do_hang: 450 ldr sp, _TEXT_BASE /* use 32 words about stack */ 451 bl hang /* hang and never return */ 452#else /* !CONFIG_SPL_BUILD */ 453 .align 5 454undefined_instruction: 455 get_bad_stack 456 bad_save_user_regs 457 bl do_undefined_instruction 458 459 .align 5 460software_interrupt: 461 get_bad_stack_swi 462 bad_save_user_regs 463 bl do_software_interrupt 464 465 .align 5 466prefetch_abort: 467 get_bad_stack 468 bad_save_user_regs 469 bl do_prefetch_abort 470 471 .align 5 472data_abort: 473 get_bad_stack 474 bad_save_user_regs 475 bl do_data_abort 476 477 .align 5 478not_used: 479 get_bad_stack 480 bad_save_user_regs 481 bl do_not_used 482 483#ifdef CONFIG_USE_IRQ 484 485 .align 5 486irq: 487 get_irq_stack 488 irq_save_user_regs 489 bl do_irq 490 irq_restore_user_regs 491 492 .align 5 493fiq: 494 get_fiq_stack 495 /* someone ought to write a more effiction fiq_save_user_regs */ 496 irq_save_user_regs 497 bl do_fiq 498 irq_restore_user_regs 499 500#else 501 502 .align 5 503irq: 504 get_bad_stack 505 bad_save_user_regs 506 bl do_irq 507 508 .align 5 509fiq: 510 get_bad_stack 511 bad_save_user_regs 512 bl do_fiq 513 514#endif 515 .align 5 516.global arm1136_cache_flush 517arm1136_cache_flush: 518#if !defined(CONFIG_SYS_ICACHE_OFF) 519 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 520#endif 521#if !defined(CONFIG_SYS_DCACHE_OFF) 522 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 523#endif 524 mov pc, lr @ back to caller 525#endif /* CONFIG_SPL_BUILD */ 526