1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007 4 * Sascha Hauer, Pengutronix 5 * 6 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/crm_regs.h> 13 14 /* General purpose timers bitfields */ 15 #define GPTCR_SWR (1<<15) /* Software reset */ 16 #define GPTCR_FRR (1<<9) /* Freerun / restart */ 17 #define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ 18 #define GPTCR_TEN (1) /* Timer enable */ 19 20 /* 21 * nothing really to do with interrupts, just starts up a counter. 22 * The 32KHz 32-bit timer overruns in 134217 seconds 23 */ 24 int timer_init(void) 25 { 26 int i; 27 struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; 28 struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; 29 30 /* setup GP Timer 1 */ 31 writel(GPTCR_SWR, &gpt->ctrl); 32 33 writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); 34 35 for (i = 0; i < 100; i++) 36 writel(0, &gpt->ctrl); /* We have no udelay by now */ 37 writel(0, &gpt->pre); /* prescaler = 1 */ 38 /* Freerun Mode, 32KHz input */ 39 writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, 40 &gpt->ctrl); 41 writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); 42 43 return 0; 44 } 45