1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/crm_regs.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 /* General purpose timers bitfields */ 18 #define GPTCR_SWR (1<<15) /* Software reset */ 19 #define GPTCR_FRR (1<<9) /* Freerun / restart */ 20 #define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ 21 #define GPTCR_TEN (1) /* Timer enable */ 22 23 /* 24 * nothing really to do with interrupts, just starts up a counter. 25 * The 32KHz 32-bit timer overruns in 134217 seconds 26 */ 27 int timer_init(void) 28 { 29 int i; 30 struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; 31 struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; 32 33 /* setup GP Timer 1 */ 34 writel(GPTCR_SWR, &gpt->ctrl); 35 36 writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); 37 38 for (i = 0; i < 100; i++) 39 writel(0, &gpt->ctrl); /* We have no udelay by now */ 40 writel(0, &gpt->pre); /* prescaler = 1 */ 41 /* Freerun Mode, 32KHz input */ 42 writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, 43 &gpt->ctrl); 44 writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); 45 46 return 0; 47 } 48