1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/io.h> 28 #include <asm/errno.h> 29 #include <asm/arch/imx-regs.h> 30 #include <asm/arch/crm_regs.h> 31 #include <asm/arch/clock.h> 32 #include <asm/arch/sys_proto.h> 33 #ifdef CONFIG_FSL_ESDHC 34 #include <fsl_esdhc.h> 35 #endif 36 #include <netdev.h> 37 38 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) 39 #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) 40 #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) 41 #define CLK_CODE_PATH(c) ((c) & 0xFF) 42 43 #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) 44 45 #ifdef CONFIG_FSL_ESDHC 46 DECLARE_GLOBAL_DATA_PTR; 47 #endif 48 49 static int g_clk_mux_auto[8] = { 50 CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, 51 CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, 52 }; 53 54 static int g_clk_mux_consumer[16] = { 55 CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, 56 -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), 57 CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, 58 -1, -1, CLK_CODE(4, 2, 0), -1, 59 }; 60 61 static int hsp_div_table[3][16] = { 62 {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, 63 {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, 64 {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, 65 }; 66 67 u32 get_cpu_rev(void) 68 { 69 int reg; 70 struct iim_regs *iim = 71 (struct iim_regs *)IIM_BASE_ADDR; 72 reg = readl(&iim->iim_srev); 73 if (!reg) { 74 reg = readw(ROMPATCH_REV); 75 reg <<= 4; 76 } else { 77 reg += CHIP_REV_1_0; 78 } 79 80 return 0x35000 + (reg & 0xFF); 81 } 82 83 static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) 84 { 85 int *pclk_mux; 86 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { 87 pclk_mux = g_clk_mux_consumer + 88 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> 89 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); 90 } else { 91 pclk_mux = g_clk_mux_auto + 92 ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> 93 MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); 94 } 95 96 if ((*pclk_mux) == -1) 97 return -1; 98 99 if (fi && fd) { 100 if (!CLK_CODE_PATH(*pclk_mux)) { 101 *fi = *fd = 1; 102 return CLK_CODE_ARM(*pclk_mux); 103 } 104 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { 105 *fi = 3; 106 *fd = 4; 107 } else { 108 *fi = 2; 109 *fd = 3; 110 } 111 } 112 return CLK_CODE_ARM(*pclk_mux); 113 } 114 115 static int get_ahb_div(u32 pdr0) 116 { 117 int *pclk_mux; 118 119 pclk_mux = g_clk_mux_consumer + 120 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> 121 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); 122 123 if ((*pclk_mux) == -1) 124 return -1; 125 126 return CLK_CODE_AHB(*pclk_mux); 127 } 128 129 static u32 decode_pll(u32 reg, u32 infreq) 130 { 131 u32 mfi = (reg >> 10) & 0xf; 132 u32 mfn = reg & 0x3f; 133 u32 mfd = (reg >> 16) & 0x3f; 134 u32 pd = (reg >> 26) & 0xf; 135 136 mfi = mfi <= 5 ? 5 : mfi; 137 mfd += 1; 138 pd += 1; 139 140 return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; 141 } 142 143 static u32 get_mcu_main_clk(void) 144 { 145 u32 arm_div = 0, fi = 0, fd = 0; 146 struct ccm_regs *ccm = 147 (struct ccm_regs *)IMX_CCM_BASE; 148 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); 149 fi *= 150 decode_pll(readl(&ccm->mpctl), 151 CONFIG_MX35_HCLK_FREQ); 152 return fi / (arm_div * fd); 153 } 154 155 static u32 get_ipg_clk(void) 156 { 157 u32 freq = get_mcu_main_clk(); 158 struct ccm_regs *ccm = 159 (struct ccm_regs *)IMX_CCM_BASE; 160 u32 pdr0 = readl(&ccm->pdr0); 161 162 return freq / (get_ahb_div(pdr0) * 2); 163 } 164 165 static u32 get_ipg_per_clk(void) 166 { 167 u32 freq = get_mcu_main_clk(); 168 struct ccm_regs *ccm = 169 (struct ccm_regs *)IMX_CCM_BASE; 170 u32 pdr0 = readl(&ccm->pdr0); 171 u32 pdr4 = readl(&ccm->pdr4); 172 u32 div; 173 if (pdr0 & MXC_CCM_PDR0_PER_SEL) { 174 div = (CCM_GET_DIVIDER(pdr4, 175 MXC_CCM_PDR4_PER0_PRDF_MASK, 176 MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * 177 (CCM_GET_DIVIDER(pdr4, 178 MXC_CCM_PDR4_PER0_PODF_MASK, 179 MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); 180 } else { 181 div = CCM_GET_DIVIDER(pdr0, 182 MXC_CCM_PDR0_PER_PODF_MASK, 183 MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; 184 freq /= get_ahb_div(pdr0); 185 } 186 return freq / div; 187 } 188 189 u32 imx_get_uartclk(void) 190 { 191 u32 freq; 192 struct ccm_regs *ccm = 193 (struct ccm_regs *)IMX_CCM_BASE; 194 u32 pdr4 = readl(&ccm->pdr4); 195 196 if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { 197 freq = get_mcu_main_clk(); 198 } else { 199 freq = decode_pll(readl(&ccm->ppctl), 200 CONFIG_MX35_HCLK_FREQ); 201 } 202 freq /= ((CCM_GET_DIVIDER(pdr4, 203 MXC_CCM_PDR4_UART_PRDF_MASK, 204 MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * 205 (CCM_GET_DIVIDER(pdr4, 206 MXC_CCM_PDR4_UART_PODF_MASK, 207 MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); 208 return freq; 209 } 210 211 unsigned int mxc_get_main_clock(enum mxc_main_clock clk) 212 { 213 u32 nfc_pdf, hsp_podf; 214 u32 pll, ret_val = 0, usb_prdf, usb_podf; 215 struct ccm_regs *ccm = 216 (struct ccm_regs *)IMX_CCM_BASE; 217 218 u32 reg = readl(&ccm->pdr0); 219 u32 reg4 = readl(&ccm->pdr4); 220 221 reg |= 0x1; 222 223 switch (clk) { 224 case CPU_CLK: 225 ret_val = get_mcu_main_clk(); 226 break; 227 case AHB_CLK: 228 ret_val = get_mcu_main_clk(); 229 break; 230 case HSP_CLK: 231 if (reg & CLKMODE_CONSUMER) { 232 hsp_podf = (reg >> 20) & 0x3; 233 pll = get_mcu_main_clk(); 234 hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; 235 if (hsp_podf > 0) { 236 ret_val = pll / hsp_podf; 237 } else { 238 puts("mismatch HSP with ARM clock setting\n"); 239 ret_val = 0; 240 } 241 } else { 242 ret_val = get_mcu_main_clk(); 243 } 244 break; 245 case IPG_CLK: 246 ret_val = get_ipg_clk(); 247 break; 248 case IPG_PER_CLK: 249 ret_val = get_ipg_per_clk(); 250 break; 251 case NFC_CLK: 252 nfc_pdf = (reg4 >> 28) & 0xF; 253 pll = get_mcu_main_clk(); 254 /* AHB/nfc_pdf */ 255 ret_val = pll / (nfc_pdf + 1); 256 break; 257 case USB_CLK: 258 usb_prdf = (reg4 >> 25) & 0x7; 259 usb_podf = (reg4 >> 22) & 0x7; 260 if (reg4 & 0x200) { 261 pll = get_mcu_main_clk(); 262 } else { 263 pll = decode_pll(readl(&ccm->ppctl), 264 CONFIG_MX35_HCLK_FREQ); 265 } 266 267 ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); 268 break; 269 default: 270 printf("Unknown clock: %d\n", clk); 271 break; 272 } 273 274 return ret_val; 275 } 276 unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) 277 { 278 u32 ret_val = 0, pdf, pre_pdf, clk_sel; 279 struct ccm_regs *ccm = 280 (struct ccm_regs *)IMX_CCM_BASE; 281 u32 mpdr2 = readl(&ccm->pdr2); 282 u32 mpdr3 = readl(&ccm->pdr3); 283 u32 mpdr4 = readl(&ccm->pdr4); 284 285 switch (clk) { 286 case UART1_BAUD: 287 case UART2_BAUD: 288 case UART3_BAUD: 289 clk_sel = mpdr3 & (1 << 14); 290 pre_pdf = (mpdr4 >> 13) & 0x7; 291 pdf = (mpdr4 >> 10) & 0x7; 292 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 293 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 294 ((pre_pdf + 1) * (pdf + 1)); 295 break; 296 case SSI1_BAUD: 297 pre_pdf = (mpdr2 >> 24) & 0x7; 298 pdf = mpdr2 & 0x3F; 299 clk_sel = mpdr2 & (1 << 6); 300 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 301 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 302 ((pre_pdf + 1) * (pdf + 1)); 303 break; 304 case SSI2_BAUD: 305 pre_pdf = (mpdr2 >> 27) & 0x7; 306 pdf = (mpdr2 >> 8) & 0x3F; 307 clk_sel = mpdr2 & (1 << 6); 308 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 309 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 310 ((pre_pdf + 1) * (pdf + 1)); 311 break; 312 case CSI_BAUD: 313 clk_sel = mpdr2 & (1 << 7); 314 pre_pdf = (mpdr2 >> 16) & 0x7; 315 pdf = (mpdr2 >> 19) & 0x7; 316 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 317 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 318 ((pre_pdf + 1) * (pdf + 1)); 319 break; 320 case MSHC_CLK: 321 pre_pdf = readl(&ccm->pdr1); 322 clk_sel = (pre_pdf & 0x80); 323 pdf = (pre_pdf >> 22) & 0x3F; 324 pre_pdf = (pre_pdf >> 28) & 0x7; 325 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 326 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 327 ((pre_pdf + 1) * (pdf + 1)); 328 break; 329 case ESDHC1_CLK: 330 clk_sel = mpdr3 & 0x40; 331 pre_pdf = mpdr3 & 0x7; 332 pdf = (mpdr3>>3) & 0x7; 333 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 334 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 335 ((pre_pdf + 1) * (pdf + 1)); 336 break; 337 case ESDHC2_CLK: 338 clk_sel = mpdr3 & 0x40; 339 pre_pdf = (mpdr3 >> 8) & 0x7; 340 pdf = (mpdr3 >> 11) & 0x7; 341 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 342 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 343 ((pre_pdf + 1) * (pdf + 1)); 344 break; 345 case ESDHC3_CLK: 346 clk_sel = mpdr3 & 0x40; 347 pre_pdf = (mpdr3 >> 16) & 0x7; 348 pdf = (mpdr3 >> 19) & 0x7; 349 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 350 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 351 ((pre_pdf + 1) * (pdf + 1)); 352 break; 353 case SPDIF_CLK: 354 clk_sel = mpdr3 & 0x400000; 355 pre_pdf = (mpdr3 >> 29) & 0x7; 356 pdf = (mpdr3 >> 23) & 0x3F; 357 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 358 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 359 ((pre_pdf + 1) * (pdf + 1)); 360 break; 361 default: 362 printf("%s(): This clock: %d not supported yet\n", 363 __func__, clk); 364 break; 365 } 366 367 return ret_val; 368 } 369 370 unsigned int mxc_get_clock(enum mxc_clock clk) 371 { 372 switch (clk) { 373 case MXC_ARM_CLK: 374 return get_mcu_main_clk(); 375 case MXC_AHB_CLK: 376 break; 377 case MXC_IPG_CLK: 378 return get_ipg_clk(); 379 case MXC_IPG_PERCLK: 380 return get_ipg_per_clk(); 381 case MXC_UART_CLK: 382 return imx_get_uartclk(); 383 case MXC_ESDHC_CLK: 384 return mxc_get_peri_clock(ESDHC1_CLK); 385 case MXC_USB_CLK: 386 return mxc_get_main_clock(USB_CLK); 387 case MXC_FEC_CLK: 388 return get_ipg_clk(); 389 case MXC_CSPI_CLK: 390 return get_ipg_clk(); 391 } 392 return -1; 393 } 394 395 #ifdef CONFIG_FEC_MXC 396 /* 397 * The MX35 has no fuse for MAC, return a NULL MAC 398 */ 399 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 400 { 401 memset(mac, 0, 6); 402 } 403 404 u32 imx_get_fecclk(void) 405 { 406 return mxc_get_clock(MXC_IPG_CLK); 407 } 408 #endif 409 410 int do_mx35_showclocks(cmd_tbl_t *cmdtp, 411 int flag, int argc, char * const argv[]) 412 { 413 u32 cpufreq = get_mcu_main_clk(); 414 printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); 415 printf("ipg clock : %dHz\n", get_ipg_clk()); 416 printf("ipg per clock : %dHz\n", get_ipg_per_clk()); 417 printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); 418 419 return 0; 420 } 421 422 U_BOOT_CMD( 423 clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, 424 "display clocks", 425 "" 426 ); 427 428 #if defined(CONFIG_DISPLAY_CPUINFO) 429 static char *get_reset_cause(void) 430 { 431 /* read RCSR register from CCM module */ 432 struct ccm_regs *ccm = 433 (struct ccm_regs *)IMX_CCM_BASE; 434 435 u32 cause = readl(&ccm->rcsr) & 0x0F; 436 437 switch (cause) { 438 case 0x0000: 439 return "POR"; 440 case 0x0002: 441 return "JTAG"; 442 case 0x0004: 443 return "RST"; 444 case 0x0008: 445 return "WDOG"; 446 default: 447 return "unknown reset"; 448 } 449 } 450 451 int print_cpuinfo(void) 452 { 453 u32 srev = get_cpu_rev(); 454 455 printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n", 456 (srev & 0xF0) >> 4, (srev & 0x0F), 457 get_mcu_main_clk() / 1000000); 458 459 printf("Reset cause: %s\n", get_reset_cause()); 460 461 return 0; 462 } 463 #endif 464 465 /* 466 * Initializes on-chip ethernet controllers. 467 * to override, implement board_eth_init() 468 */ 469 int cpu_eth_init(bd_t *bis) 470 { 471 int rc = -ENODEV; 472 473 #if defined(CONFIG_FEC_MXC) 474 rc = fecmxc_initialize(bis); 475 #endif 476 477 return rc; 478 } 479 480 #ifdef CONFIG_FSL_ESDHC 481 /* 482 * Initializes on-chip MMC controllers. 483 * to override, implement board_mmc_init() 484 */ 485 int cpu_mmc_init(bd_t *bis) 486 { 487 return fsl_esdhc_mmc_init(bis); 488 } 489 #endif 490 491 int get_clocks(void) 492 { 493 #ifdef CONFIG_FSL_ESDHC 494 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 495 #endif 496 return 0; 497 } 498 499 void reset_cpu(ulong addr) 500 { 501 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; 502 writew(4, &wdog->wcr); 503 } 504