1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <div64.h> 28 #include <asm/io.h> 29 #include <asm/errno.h> 30 #include <asm/arch/imx-regs.h> 31 #include <asm/arch/crm_regs.h> 32 #include <asm/arch/clock.h> 33 #include <asm/arch/sys_proto.h> 34 #ifdef CONFIG_FSL_ESDHC 35 #include <fsl_esdhc.h> 36 #endif 37 #include <netdev.h> 38 39 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) 40 #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) 41 #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) 42 #define CLK_CODE_PATH(c) ((c) & 0xFF) 43 44 #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) 45 46 #ifdef CONFIG_FSL_ESDHC 47 DECLARE_GLOBAL_DATA_PTR; 48 #endif 49 50 static int g_clk_mux_auto[8] = { 51 CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, 52 CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, 53 }; 54 55 static int g_clk_mux_consumer[16] = { 56 CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, 57 -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), 58 CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, 59 -1, -1, CLK_CODE(4, 2, 0), -1, 60 }; 61 62 static int hsp_div_table[3][16] = { 63 {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, 64 {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, 65 {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, 66 }; 67 68 u32 get_cpu_rev(void) 69 { 70 int reg; 71 struct iim_regs *iim = 72 (struct iim_regs *)IIM_BASE_ADDR; 73 reg = readl(&iim->iim_srev); 74 if (!reg) { 75 reg = readw(ROMPATCH_REV); 76 reg <<= 4; 77 } else { 78 reg += CHIP_REV_1_0; 79 } 80 81 return 0x35000 + (reg & 0xFF); 82 } 83 84 static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) 85 { 86 int *pclk_mux; 87 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { 88 pclk_mux = g_clk_mux_consumer + 89 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> 90 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); 91 } else { 92 pclk_mux = g_clk_mux_auto + 93 ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> 94 MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); 95 } 96 97 if ((*pclk_mux) == -1) 98 return -1; 99 100 if (fi && fd) { 101 if (!CLK_CODE_PATH(*pclk_mux)) { 102 *fi = *fd = 1; 103 return CLK_CODE_ARM(*pclk_mux); 104 } 105 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { 106 *fi = 3; 107 *fd = 4; 108 } else { 109 *fi = 2; 110 *fd = 3; 111 } 112 } 113 return CLK_CODE_ARM(*pclk_mux); 114 } 115 116 static int get_ahb_div(u32 pdr0) 117 { 118 int *pclk_mux; 119 120 pclk_mux = g_clk_mux_consumer + 121 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> 122 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); 123 124 if ((*pclk_mux) == -1) 125 return -1; 126 127 return CLK_CODE_AHB(*pclk_mux); 128 } 129 130 static u32 decode_pll(u32 reg, u32 infreq) 131 { 132 u32 mfi = (reg >> 10) & 0xf; 133 s32 mfn = reg & 0x3ff; 134 u32 mfd = (reg >> 16) & 0x3ff; 135 u32 pd = (reg >> 26) & 0xf; 136 137 mfi = mfi <= 5 ? 5 : mfi; 138 mfn = mfn >= 512 ? mfn - 1024 : mfn; 139 mfd += 1; 140 pd += 1; 141 142 return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), 143 mfd * pd); 144 } 145 146 static u32 get_mcu_main_clk(void) 147 { 148 u32 arm_div = 0, fi = 0, fd = 0; 149 struct ccm_regs *ccm = 150 (struct ccm_regs *)IMX_CCM_BASE; 151 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); 152 fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); 153 return fi / (arm_div * fd); 154 } 155 156 static u32 get_ipg_clk(void) 157 { 158 u32 freq = get_mcu_main_clk(); 159 struct ccm_regs *ccm = 160 (struct ccm_regs *)IMX_CCM_BASE; 161 u32 pdr0 = readl(&ccm->pdr0); 162 163 return freq / (get_ahb_div(pdr0) * 2); 164 } 165 166 static u32 get_ipg_per_clk(void) 167 { 168 u32 freq = get_mcu_main_clk(); 169 struct ccm_regs *ccm = 170 (struct ccm_regs *)IMX_CCM_BASE; 171 u32 pdr0 = readl(&ccm->pdr0); 172 u32 pdr4 = readl(&ccm->pdr4); 173 u32 div; 174 if (pdr0 & MXC_CCM_PDR0_PER_SEL) { 175 div = CCM_GET_DIVIDER(pdr4, 176 MXC_CCM_PDR4_PER0_PODF_MASK, 177 MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; 178 } else { 179 div = CCM_GET_DIVIDER(pdr0, 180 MXC_CCM_PDR0_PER_PODF_MASK, 181 MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; 182 div *= get_ahb_div(pdr0); 183 } 184 return freq / div; 185 } 186 187 u32 imx_get_uartclk(void) 188 { 189 u32 freq; 190 struct ccm_regs *ccm = 191 (struct ccm_regs *)IMX_CCM_BASE; 192 u32 pdr4 = readl(&ccm->pdr4); 193 194 if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) 195 freq = get_mcu_main_clk(); 196 else 197 freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); 198 freq /= CCM_GET_DIVIDER(pdr4, 199 MXC_CCM_PDR4_UART_PODF_MASK, 200 MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; 201 return freq; 202 } 203 204 unsigned int mxc_get_main_clock(enum mxc_main_clock clk) 205 { 206 u32 nfc_pdf, hsp_podf; 207 u32 pll, ret_val = 0, usb_podf; 208 struct ccm_regs *ccm = 209 (struct ccm_regs *)IMX_CCM_BASE; 210 211 u32 reg = readl(&ccm->pdr0); 212 u32 reg4 = readl(&ccm->pdr4); 213 214 reg |= 0x1; 215 216 switch (clk) { 217 case CPU_CLK: 218 ret_val = get_mcu_main_clk(); 219 break; 220 case AHB_CLK: 221 ret_val = get_mcu_main_clk(); 222 break; 223 case HSP_CLK: 224 if (reg & CLKMODE_CONSUMER) { 225 hsp_podf = (reg >> 20) & 0x3; 226 pll = get_mcu_main_clk(); 227 hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; 228 if (hsp_podf > 0) { 229 ret_val = pll / hsp_podf; 230 } else { 231 puts("mismatch HSP with ARM clock setting\n"); 232 ret_val = 0; 233 } 234 } else { 235 ret_val = get_mcu_main_clk(); 236 } 237 break; 238 case IPG_CLK: 239 ret_val = get_ipg_clk(); 240 break; 241 case IPG_PER_CLK: 242 ret_val = get_ipg_per_clk(); 243 break; 244 case NFC_CLK: 245 nfc_pdf = (reg4 >> 28) & 0xF; 246 pll = get_mcu_main_clk(); 247 /* AHB/nfc_pdf */ 248 ret_val = pll / (nfc_pdf + 1); 249 break; 250 case USB_CLK: 251 usb_podf = (reg4 >> 22) & 0x3F; 252 if (reg4 & 0x200) 253 pll = get_mcu_main_clk(); 254 else 255 pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK); 256 257 ret_val = pll / (usb_podf + 1); 258 break; 259 default: 260 printf("Unknown clock: %d\n", clk); 261 break; 262 } 263 264 return ret_val; 265 } 266 unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) 267 { 268 u32 ret_val = 0, pdf, pre_pdf, clk_sel; 269 struct ccm_regs *ccm = 270 (struct ccm_regs *)IMX_CCM_BASE; 271 u32 mpdr2 = readl(&ccm->pdr2); 272 u32 mpdr3 = readl(&ccm->pdr3); 273 u32 mpdr4 = readl(&ccm->pdr4); 274 275 switch (clk) { 276 case UART1_BAUD: 277 case UART2_BAUD: 278 case UART3_BAUD: 279 clk_sel = mpdr3 & (1 << 14); 280 pdf = (mpdr4 >> 10) & 0x3F; 281 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 282 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); 283 break; 284 case SSI1_BAUD: 285 pre_pdf = (mpdr2 >> 24) & 0x7; 286 pdf = mpdr2 & 0x3F; 287 clk_sel = mpdr2 & (1 << 6); 288 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 289 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / 290 ((pre_pdf + 1) * (pdf + 1)); 291 break; 292 case SSI2_BAUD: 293 pre_pdf = (mpdr2 >> 27) & 0x7; 294 pdf = (mpdr2 >> 8) & 0x3F; 295 clk_sel = mpdr2 & (1 << 6); 296 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 297 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / 298 ((pre_pdf + 1) * (pdf + 1)); 299 break; 300 case CSI_BAUD: 301 clk_sel = mpdr2 & (1 << 7); 302 pdf = (mpdr2 >> 16) & 0x3F; 303 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 304 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); 305 break; 306 case MSHC_CLK: 307 pre_pdf = readl(&ccm->pdr1); 308 clk_sel = (pre_pdf & 0x80); 309 pdf = (pre_pdf >> 22) & 0x3F; 310 pre_pdf = (pre_pdf >> 28) & 0x7; 311 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 312 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / 313 ((pre_pdf + 1) * (pdf + 1)); 314 break; 315 case ESDHC1_CLK: 316 clk_sel = mpdr3 & 0x40; 317 pdf = mpdr3 & 0x3F; 318 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 319 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); 320 break; 321 case ESDHC2_CLK: 322 clk_sel = mpdr3 & 0x40; 323 pdf = (mpdr3 >> 8) & 0x3F; 324 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 325 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); 326 break; 327 case ESDHC3_CLK: 328 clk_sel = mpdr3 & 0x40; 329 pdf = (mpdr3 >> 16) & 0x3F; 330 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 331 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); 332 break; 333 case SPDIF_CLK: 334 clk_sel = mpdr3 & 0x400000; 335 pre_pdf = (mpdr3 >> 29) & 0x7; 336 pdf = (mpdr3 >> 23) & 0x3F; 337 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 338 decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / 339 ((pre_pdf + 1) * (pdf + 1)); 340 break; 341 default: 342 printf("%s(): This clock: %d not supported yet\n", 343 __func__, clk); 344 break; 345 } 346 347 return ret_val; 348 } 349 350 unsigned int mxc_get_clock(enum mxc_clock clk) 351 { 352 switch (clk) { 353 case MXC_ARM_CLK: 354 return get_mcu_main_clk(); 355 case MXC_AHB_CLK: 356 break; 357 case MXC_IPG_CLK: 358 return get_ipg_clk(); 359 case MXC_IPG_PERCLK: 360 case MXC_I2C_CLK: 361 return get_ipg_per_clk(); 362 case MXC_UART_CLK: 363 return imx_get_uartclk(); 364 case MXC_ESDHC1_CLK: 365 return mxc_get_peri_clock(ESDHC1_CLK); 366 case MXC_ESDHC2_CLK: 367 return mxc_get_peri_clock(ESDHC2_CLK); 368 case MXC_ESDHC3_CLK: 369 return mxc_get_peri_clock(ESDHC3_CLK); 370 case MXC_USB_CLK: 371 return mxc_get_main_clock(USB_CLK); 372 case MXC_FEC_CLK: 373 return get_ipg_clk(); 374 case MXC_CSPI_CLK: 375 return get_ipg_clk(); 376 } 377 return -1; 378 } 379 380 #ifdef CONFIG_FEC_MXC 381 /* 382 * The MX35 has no fuse for MAC, return a NULL MAC 383 */ 384 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 385 { 386 memset(mac, 0, 6); 387 } 388 389 u32 imx_get_fecclk(void) 390 { 391 return mxc_get_clock(MXC_IPG_CLK); 392 } 393 #endif 394 395 int do_mx35_showclocks(cmd_tbl_t *cmdtp, 396 int flag, int argc, char * const argv[]) 397 { 398 u32 cpufreq = get_mcu_main_clk(); 399 printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); 400 printf("ipg clock : %dHz\n", get_ipg_clk()); 401 printf("ipg per clock : %dHz\n", get_ipg_per_clk()); 402 printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); 403 404 return 0; 405 } 406 407 U_BOOT_CMD( 408 clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, 409 "display clocks", 410 "" 411 ); 412 413 #if defined(CONFIG_DISPLAY_CPUINFO) 414 static char *get_reset_cause(void) 415 { 416 /* read RCSR register from CCM module */ 417 struct ccm_regs *ccm = 418 (struct ccm_regs *)IMX_CCM_BASE; 419 420 u32 cause = readl(&ccm->rcsr) & 0x0F; 421 422 switch (cause) { 423 case 0x0000: 424 return "POR"; 425 case 0x0002: 426 return "JTAG"; 427 case 0x0004: 428 return "RST"; 429 case 0x0008: 430 return "WDOG"; 431 default: 432 return "unknown reset"; 433 } 434 } 435 436 int print_cpuinfo(void) 437 { 438 u32 srev = get_cpu_rev(); 439 440 printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n", 441 (srev & 0xF0) >> 4, (srev & 0x0F), 442 get_mcu_main_clk() / 1000000); 443 444 printf("Reset cause: %s\n", get_reset_cause()); 445 446 return 0; 447 } 448 #endif 449 450 /* 451 * Initializes on-chip ethernet controllers. 452 * to override, implement board_eth_init() 453 */ 454 int cpu_eth_init(bd_t *bis) 455 { 456 int rc = -ENODEV; 457 458 #if defined(CONFIG_FEC_MXC) 459 rc = fecmxc_initialize(bis); 460 #endif 461 462 return rc; 463 } 464 465 #ifdef CONFIG_FSL_ESDHC 466 /* 467 * Initializes on-chip MMC controllers. 468 * to override, implement board_mmc_init() 469 */ 470 int cpu_mmc_init(bd_t *bis) 471 { 472 return fsl_esdhc_mmc_init(bis); 473 } 474 #endif 475 476 int get_clocks(void) 477 { 478 #ifdef CONFIG_FSL_ESDHC 479 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR 480 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 481 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR 482 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 483 #else 484 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); 485 #endif 486 #endif 487 return 0; 488 } 489 490 void reset_cpu(ulong addr) 491 { 492 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; 493 writew(4, &wdog->wcr); 494 } 495