xref: /openbmc/u-boot/arch/arm/cpu/arm1136/mx31/timer.c (revision fea7f3aa)
1 /*
2  * (C) Copyright 2007
3  * Sascha Hauer, Pengutronix
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/io.h>
11 
12 #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
13 
14 /* General purpose timers registers */
15 #define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
16 #define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
17 #define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
18 #define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
19 
20 /* General purpose timers bitfields */
21 #define GPTCR_SWR		(1 << 15)	/* Software reset	*/
22 #define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
23 #define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
24 #define GPTCR_TEN		1		/* Timer enable		*/
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 /* The 32768Hz 32-bit timer overruns in 131072 seconds */
29 int timer_init(void)
30 {
31 	int i;
32 
33 	/* setup GP Timer 1 */
34 	GPTCR = GPTCR_SWR;
35 	for (i = 0; i < 100; i++)
36 		GPTCR = 0; /* We have no udelay by now */
37 	GPTPR = 0; /* 32Khz */
38 	/* Freerun Mode, PERCLK1 input */
39 	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
40 
41 	return 0;
42 }
43 
44 unsigned long timer_read_counter(void)
45 {
46 	return GPTCNT;
47 }
48