1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/arch/imx-regs.h> 26 #include <div64.h> 27 #include <watchdog.h> 28 #include <asm/io.h> 29 30 #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ 31 32 /* General purpose timers registers */ 33 #define GPTCR __REG(TIMER_BASE) /* Control register */ 34 #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ 35 #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ 36 #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ 37 38 /* General purpose timers bitfields */ 39 #define GPTCR_SWR (1 << 15) /* Software reset */ 40 #define GPTCR_FRR (1 << 9) /* Freerun / restart */ 41 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ 42 #define GPTCR_TEN 1 /* Timer enable */ 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 /* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ 47 #ifdef CONFIG_MX31_TIMER_HIGH_PRECISION 48 /* ~0.4% error - measured with stop-watch on 100s boot-delay */ 49 static inline unsigned long long tick_to_time(unsigned long long tick) 50 { 51 tick *= CONFIG_SYS_HZ; 52 do_div(tick, CONFIG_MX31_CLK32); 53 return tick; 54 } 55 56 static inline unsigned long long time_to_tick(unsigned long long time) 57 { 58 time *= CONFIG_MX31_CLK32; 59 do_div(time, CONFIG_SYS_HZ); 60 return time; 61 } 62 63 static inline unsigned long long us_to_tick(unsigned long long us) 64 { 65 us = us * CONFIG_MX31_CLK32 + 999999; 66 do_div(us, 1000000); 67 return us; 68 } 69 #else 70 /* ~2% error */ 71 #define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) 72 #define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) 73 74 static inline unsigned long long tick_to_time(unsigned long long tick) 75 { 76 do_div(tick, TICK_PER_TIME); 77 return tick; 78 } 79 80 static inline unsigned long long time_to_tick(unsigned long long time) 81 { 82 return time * TICK_PER_TIME; 83 } 84 85 static inline unsigned long long us_to_tick(unsigned long long us) 86 { 87 us += US_PER_TICK - 1; 88 do_div(us, US_PER_TICK); 89 return us; 90 } 91 #endif 92 93 /* The 32768Hz 32-bit timer overruns in 131072 seconds */ 94 int timer_init (void) 95 { 96 int i; 97 98 /* setup GP Timer 1 */ 99 GPTCR = GPTCR_SWR; 100 for (i = 0; i < 100; i++) 101 GPTCR = 0; /* We have no udelay by now */ 102 GPTPR = 0; /* 32Khz */ 103 /* Freerun Mode, PERCLK1 input */ 104 GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; 105 106 return 0; 107 } 108 109 void reset_timer_masked (void) 110 { 111 /* reset time */ 112 gd->lastinc = GPTCNT; /* capture current incrementer value time */ 113 gd->tbl = 0; /* start "advancing" time stamp from 0 */ 114 } 115 116 void reset_timer(void) 117 { 118 reset_timer_masked(); 119 } 120 121 unsigned long long get_ticks (void) 122 { 123 ulong now = GPTCNT; /* current tick value */ 124 125 if (now >= gd->lastinc) /* normal mode (non roll) */ 126 /* move stamp forward with absolut diff ticks */ 127 gd->tbl += (now - gd->lastinc); 128 else /* we have rollover of incrementer */ 129 gd->tbl += (0xFFFFFFFF - gd->lastinc) + now; 130 gd->lastinc = now; 131 return gd->tbl; 132 } 133 134 ulong get_timer_masked (void) 135 { 136 /* 137 * get_ticks() returns a long long (64 bit), it wraps in 138 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ 139 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in 140 * 5 * 10^6 days - long enough. 141 */ 142 return tick_to_time(get_ticks()); 143 } 144 145 ulong get_timer (ulong base) 146 { 147 return get_timer_masked () - base; 148 } 149 150 /* delay x useconds AND preserve advance timestamp value */ 151 void __udelay (unsigned long usec) 152 { 153 unsigned long long tmp; 154 ulong tmo; 155 156 tmo = us_to_tick(usec); 157 tmp = get_ticks() + tmo; /* get current timestamp */ 158 159 while (get_ticks() < tmp) /* loop till event */ 160 /*NOP*/; 161 } 162 163 void reset_cpu (ulong addr) 164 { 165 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; 166 wdog->wcr = WDOG_ENABLE; 167 while (1) 168 ; 169 } 170 171 #ifdef CONFIG_HW_WATCHDOG 172 void mxc_hw_watchdog_enable(void) 173 { 174 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; 175 u16 secs; 176 177 /* 178 * The timer watchdog can be set between 179 * 0.5 and 128 Seconds. If not defined 180 * in configuration file, sets 64 Seconds 181 */ 182 #ifdef CONFIG_SYS_WD_TIMER_SECS 183 secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF; 184 if (!secs) secs = 1; 185 #else 186 secs = 64; 187 #endif 188 writew(readw(&wdog->wcr) | (secs << WDOG_WT_SHIFT) | WDOG_ENABLE, 189 &wdog->wcr); 190 } 191 192 193 void mxc_hw_watchdog_reset(void) 194 { 195 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; 196 197 writew(0x5555, &wdog->wsr); 198 writew(0xAAAA, &wdog->wsr); 199 } 200 #endif 201