1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/io.h> 27 28 static u32 mx31_decode_pll(u32 reg, u32 infreq) 29 { 30 u32 mfi = (reg >> 10) & 0xf; 31 u32 mfn = reg & 0x3ff; 32 u32 mfd = (reg >> 16) & 0x3ff; 33 u32 pd = (reg >> 26) & 0xf; 34 35 mfi = mfi <= 5 ? 5 : mfi; 36 mfd += 1; 37 pd += 1; 38 39 return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / 40 (mfd * pd)) << 10; 41 } 42 43 static u32 mx31_get_mpl_dpdgck_clk(void) 44 { 45 u32 infreq; 46 47 if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) 48 infreq = CONFIG_MX31_CLK32 * 1024; 49 else 50 infreq = CONFIG_MX31_HCLK_FREQ; 51 52 return mx31_decode_pll(__REG(CCM_MPCTL), infreq); 53 } 54 55 static u32 mx31_get_mcu_main_clk(void) 56 { 57 /* For now we assume mpl_dpdgck_clk == mcu_main_clk 58 * which should be correct for most boards 59 */ 60 return mx31_get_mpl_dpdgck_clk(); 61 } 62 63 u32 mx31_get_ipg_clk(void) 64 { 65 u32 freq = mx31_get_mcu_main_clk(); 66 u32 pdr0 = __REG(CCM_PDR0); 67 68 freq /= ((pdr0 >> 3) & 0x7) + 1; 69 freq /= ((pdr0 >> 6) & 0x3) + 1; 70 71 return freq; 72 } 73 74 void mx31_dump_clocks(void) 75 { 76 u32 cpufreq = mx31_get_mcu_main_clk(); 77 printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); 78 printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); 79 } 80 81 void mx31_gpio_mux(unsigned long mode) 82 { 83 unsigned long reg, shift, tmp; 84 85 reg = IOMUXC_BASE + (mode & 0x1fc); 86 shift = (~mode & 0x3) * 8; 87 88 tmp = __REG(reg); 89 tmp &= ~(0xff << shift); 90 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift; 91 __REG(reg) = tmp; 92 } 93 94 void mx31_set_pad(enum iomux_pins pin, u32 config) 95 { 96 u32 field, l, reg; 97 98 pin &= IOMUX_PADNUM_MASK; 99 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4; 100 field = (pin + 2) % 3; 101 102 l = __REG(reg); 103 l &= ~(0x1ff << (field * 10)); 104 l |= config << (field * 10); 105 __REG(reg) = l; 106 107 } 108 109 struct mx3_cpu_type mx31_cpu_type[] = { 110 { .srev = 0x00, .v = 0x10 }, 111 { .srev = 0x10, .v = 0x11 }, 112 { .srev = 0x11, .v = 0x11 }, 113 { .srev = 0x12, .v = 0x1F }, 114 { .srev = 0x13, .v = 0x1F }, 115 { .srev = 0x14, .v = 0x12 }, 116 { .srev = 0x15, .v = 0x12 }, 117 { .srev = 0x28, .v = 0x20 }, 118 { .srev = 0x29, .v = 0x20 }, 119 }; 120 121 u32 get_cpu_rev(void) 122 { 123 u32 i, srev; 124 125 /* read SREV register from IIM module */ 126 struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR; 127 srev = readl(&iim->iim_srev); 128 129 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) 130 if (srev == mx31_cpu_type[i].srev) 131 return mx31_cpu_type[i].v; 132 133 return srev | 0x8000; 134 } 135 136 char *get_reset_cause(void) 137 { 138 /* read RCSR register from CCM module */ 139 struct clock_control_regs *ccm = 140 (struct clock_control_regs *)CCM_BASE; 141 142 u32 cause = readl(&ccm->rcsr) & 0x07; 143 144 switch (cause) { 145 case 0x0000: 146 return "POR"; 147 break; 148 case 0x0001: 149 return "RST"; 150 break; 151 case 0x0002: 152 return "WDOG"; 153 break; 154 case 0x0006: 155 return "JTAG"; 156 break; 157 default: 158 return "unknown reset"; 159 } 160 } 161 162 #if defined(CONFIG_DISPLAY_CPUINFO) 163 int print_cpuinfo (void) 164 { 165 u32 srev = get_cpu_rev(); 166 167 printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.", 168 (srev & 0xF0) >> 4, (srev & 0x0F), 169 ((srev & 0x8000) ? " unknown" : ""), 170 mx31_get_mcu_main_clk() / 1000000); 171 printf("Reset cause: %s\n", get_reset_cause()); 172 return 0; 173 } 174 #endif 175