1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/clock.h> 27 #include <asm/io.h> 28 #include <asm/arch/sys_proto.h> 29 30 #define IOMUXGPR (IOMUXC_BASE + 0x008) 31 32 static u32 mx31_decode_pll(u32 reg, u32 infreq) 33 { 34 u32 mfi = GET_PLL_MFI(reg); 35 u32 mfn = GET_PLL_MFN(reg); 36 u32 mfd = GET_PLL_MFD(reg); 37 u32 pd = GET_PLL_PD(reg); 38 39 mfi = mfi <= 5 ? 5 : mfi; 40 mfd += 1; 41 pd += 1; 42 43 return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / 44 (mfd * pd)) << 10; 45 } 46 47 static u32 mx31_get_mpl_dpdgck_clk(void) 48 { 49 u32 infreq; 50 51 if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) 52 infreq = CONFIG_MX31_CLK32 * 1024; 53 else 54 infreq = CONFIG_MX31_HCLK_FREQ; 55 56 return mx31_decode_pll(readl(CCM_MPCTL), infreq); 57 } 58 59 static u32 mx31_get_mcu_main_clk(void) 60 { 61 /* For now we assume mpl_dpdgck_clk == mcu_main_clk 62 * which should be correct for most boards 63 */ 64 return mx31_get_mpl_dpdgck_clk(); 65 } 66 67 static u32 mx31_get_ipg_clk(void) 68 { 69 u32 freq = mx31_get_mcu_main_clk(); 70 u32 pdr0 = readl(CCM_PDR0); 71 72 freq /= GET_PDR0_MAX_PODF(pdr0) + 1; 73 freq /= GET_PDR0_IPG_PODF(pdr0) + 1; 74 75 return freq; 76 } 77 78 /* hsp is the clock for the ipu */ 79 static u32 mx31_get_hsp_clk(void) 80 { 81 u32 freq = mx31_get_mcu_main_clk(); 82 u32 pdr0 = readl(CCM_PDR0); 83 84 freq /= GET_PDR0_HSP_PODF(pdr0) + 1; 85 86 return freq; 87 } 88 89 void mx31_dump_clocks(void) 90 { 91 u32 cpufreq = mx31_get_mcu_main_clk(); 92 printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); 93 printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); 94 printf("hsp clock : %dHz\n", mx31_get_hsp_clk()); 95 } 96 97 unsigned int mxc_get_clock(enum mxc_clock clk) 98 { 99 switch (clk) { 100 case MXC_ARM_CLK: 101 return mx31_get_mcu_main_clk(); 102 case MXC_IPG_CLK: 103 case MXC_IPG_PERCLK: 104 case MXC_CSPI_CLK: 105 case MXC_UART_CLK: 106 return mx31_get_ipg_clk(); 107 case MXC_IPU_CLK: 108 return mx31_get_hsp_clk(); 109 } 110 return -1; 111 } 112 113 u32 imx_get_uartclk(void) 114 { 115 return mxc_get_clock(MXC_UART_CLK); 116 } 117 118 void mx31_gpio_mux(unsigned long mode) 119 { 120 unsigned long reg, shift, tmp; 121 122 reg = IOMUXC_BASE + (mode & 0x1fc); 123 shift = (~mode & 0x3) * 8; 124 125 tmp = readl(reg); 126 tmp &= ~(0xff << shift); 127 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift; 128 writel(tmp, reg); 129 } 130 131 void mx31_set_pad(enum iomux_pins pin, u32 config) 132 { 133 u32 field, l, reg; 134 135 pin &= IOMUX_PADNUM_MASK; 136 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4; 137 field = (pin + 2) % 3; 138 139 l = readl(reg); 140 l &= ~(0x1ff << (field * 10)); 141 l |= config << (field * 10); 142 writel(l, reg); 143 144 } 145 146 void mx31_set_gpr(enum iomux_gp_func gp, char en) 147 { 148 u32 l; 149 150 l = readl(IOMUXGPR); 151 if (en) 152 l |= gp; 153 else 154 l &= ~gp; 155 156 writel(l, IOMUXGPR); 157 } 158 159 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) 160 { 161 struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE; 162 struct mx31_weim_cscr *cscr = &weim->cscr[cs]; 163 164 writel(weimcs->upper, &cscr->upper); 165 writel(weimcs->lower, &cscr->lower); 166 writel(weimcs->additional, &cscr->additional); 167 } 168 169 struct mx3_cpu_type mx31_cpu_type[] = { 170 { .srev = 0x00, .v = 0x10 }, 171 { .srev = 0x10, .v = 0x11 }, 172 { .srev = 0x11, .v = 0x11 }, 173 { .srev = 0x12, .v = 0x1F }, 174 { .srev = 0x13, .v = 0x1F }, 175 { .srev = 0x14, .v = 0x12 }, 176 { .srev = 0x15, .v = 0x12 }, 177 { .srev = 0x28, .v = 0x20 }, 178 { .srev = 0x29, .v = 0x20 }, 179 }; 180 181 u32 get_cpu_rev(void) 182 { 183 u32 i, srev; 184 185 /* read SREV register from IIM module */ 186 struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR; 187 srev = readl(&iim->iim_srev); 188 189 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) 190 if (srev == mx31_cpu_type[i].srev) 191 return mx31_cpu_type[i].v; 192 193 return srev | 0x8000; 194 } 195 196 static char *get_reset_cause(void) 197 { 198 /* read RCSR register from CCM module */ 199 struct clock_control_regs *ccm = 200 (struct clock_control_regs *)CCM_BASE; 201 202 u32 cause = readl(&ccm->rcsr) & 0x07; 203 204 switch (cause) { 205 case 0x0000: 206 return "POR"; 207 case 0x0001: 208 return "RST"; 209 case 0x0002: 210 return "WDOG"; 211 case 0x0006: 212 return "JTAG"; 213 default: 214 return "unknown reset"; 215 } 216 } 217 218 #if defined(CONFIG_DISPLAY_CPUINFO) 219 int print_cpuinfo (void) 220 { 221 u32 srev = get_cpu_rev(); 222 223 printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n", 224 (srev & 0xF0) >> 4, (srev & 0x0F), 225 ((srev & 0x8000) ? " unknown" : ""), 226 mx31_get_mcu_main_clk() / 1000000); 227 printf("Reset cause: %s\n", get_reset_cause()); 228 return 0; 229 } 230 #endif 231