1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/clock.h> 27 #include <asm/io.h> 28 29 static u32 mx31_decode_pll(u32 reg, u32 infreq) 30 { 31 u32 mfi = GET_PLL_MFI(reg); 32 u32 mfn = GET_PLL_MFN(reg); 33 u32 mfd = GET_PLL_MFD(reg); 34 u32 pd = GET_PLL_PD(reg); 35 36 mfi = mfi <= 5 ? 5 : mfi; 37 mfd += 1; 38 pd += 1; 39 40 return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / 41 (mfd * pd)) << 10; 42 } 43 44 static u32 mx31_get_mpl_dpdgck_clk(void) 45 { 46 u32 infreq; 47 48 if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) 49 infreq = CONFIG_MX31_CLK32 * 1024; 50 else 51 infreq = CONFIG_MX31_HCLK_FREQ; 52 53 return mx31_decode_pll(readl(CCM_MPCTL), infreq); 54 } 55 56 static u32 mx31_get_mcu_main_clk(void) 57 { 58 /* For now we assume mpl_dpdgck_clk == mcu_main_clk 59 * which should be correct for most boards 60 */ 61 return mx31_get_mpl_dpdgck_clk(); 62 } 63 64 static u32 mx31_get_ipg_clk(void) 65 { 66 u32 freq = mx31_get_mcu_main_clk(); 67 u32 pdr0 = readl(CCM_PDR0); 68 69 freq /= GET_PDR0_MAX_PODF(pdr0) + 1; 70 freq /= GET_PDR0_IPG_PODF(pdr0) + 1; 71 72 return freq; 73 } 74 75 /* hsp is the clock for the ipu */ 76 static u32 mx31_get_hsp_clk(void) 77 { 78 u32 freq = mx31_get_mcu_main_clk(); 79 u32 pdr0 = readl(CCM_PDR0); 80 81 freq /= GET_PDR0_HSP_PODF(pdr0) + 1; 82 83 return freq; 84 } 85 86 void mx31_dump_clocks(void) 87 { 88 u32 cpufreq = mx31_get_mcu_main_clk(); 89 printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); 90 printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); 91 printf("hsp clock : %dHz\n", mx31_get_hsp_clk()); 92 } 93 94 unsigned int mxc_get_clock(enum mxc_clock clk) 95 { 96 switch (clk) { 97 case MXC_ARM_CLK: 98 return mx31_get_mcu_main_clk(); 99 case MXC_IPG_CLK: 100 case MXC_IPG_PERCLK: 101 case MXC_CSPI_CLK: 102 case MXC_UART_CLK: 103 return mx31_get_ipg_clk(); 104 case MXC_IPU_CLK: 105 return mx31_get_hsp_clk(); 106 } 107 return -1; 108 } 109 110 u32 imx_get_uartclk(void) 111 { 112 return mxc_get_clock(MXC_UART_CLK); 113 } 114 115 void mx31_gpio_mux(unsigned long mode) 116 { 117 unsigned long reg, shift, tmp; 118 119 reg = IOMUXC_BASE + (mode & 0x1fc); 120 shift = (~mode & 0x3) * 8; 121 122 tmp = readl(reg); 123 tmp &= ~(0xff << shift); 124 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift; 125 writel(tmp, reg); 126 } 127 128 void mx31_set_pad(enum iomux_pins pin, u32 config) 129 { 130 u32 field, l, reg; 131 132 pin &= IOMUX_PADNUM_MASK; 133 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4; 134 field = (pin + 2) % 3; 135 136 l = readl(reg); 137 l &= ~(0x1ff << (field * 10)); 138 l |= config << (field * 10); 139 writel(l, reg); 140 141 } 142 143 struct mx3_cpu_type mx31_cpu_type[] = { 144 { .srev = 0x00, .v = 0x10 }, 145 { .srev = 0x10, .v = 0x11 }, 146 { .srev = 0x11, .v = 0x11 }, 147 { .srev = 0x12, .v = 0x1F }, 148 { .srev = 0x13, .v = 0x1F }, 149 { .srev = 0x14, .v = 0x12 }, 150 { .srev = 0x15, .v = 0x12 }, 151 { .srev = 0x28, .v = 0x20 }, 152 { .srev = 0x29, .v = 0x20 }, 153 }; 154 155 u32 get_cpu_rev(void) 156 { 157 u32 i, srev; 158 159 /* read SREV register from IIM module */ 160 struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR; 161 srev = readl(&iim->iim_srev); 162 163 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) 164 if (srev == mx31_cpu_type[i].srev) 165 return mx31_cpu_type[i].v; 166 167 return srev | 0x8000; 168 } 169 170 static char *get_reset_cause(void) 171 { 172 /* read RCSR register from CCM module */ 173 struct clock_control_regs *ccm = 174 (struct clock_control_regs *)CCM_BASE; 175 176 u32 cause = readl(&ccm->rcsr) & 0x07; 177 178 switch (cause) { 179 case 0x0000: 180 return "POR"; 181 case 0x0001: 182 return "RST"; 183 case 0x0002: 184 return "WDOG"; 185 case 0x0006: 186 return "JTAG"; 187 default: 188 return "unknown reset"; 189 } 190 } 191 192 #if defined(CONFIG_DISPLAY_CPUINFO) 193 int print_cpuinfo (void) 194 { 195 u32 srev = get_cpu_rev(); 196 197 printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.\n", 198 (srev & 0xF0) >> 4, (srev & 0x0F), 199 ((srev & 0x8000) ? " unknown" : ""), 200 mx31_get_mcu_main_clk() / 1000000); 201 printf("Reset cause: %s\n", get_reset_cause()); 202 return 0; 203 } 204 #endif 205