xref: /openbmc/u-boot/arch/arc/include/asm/io.h (revision ee7bb5be) 
1 /*
2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARC_IO_H
8 #define __ASM_ARC_IO_H
9 
10 #include <linux/types.h>
11 #include <asm/byteorder.h>
12 
13 /*
14  * Given a physical address and a length, return a virtual address
15  * that can be used to access the memory range with the caching
16  * properties specified by "flags".
17  */
18 #define MAP_NOCACHE	(0)
19 #define MAP_WRCOMBINE	(0)
20 #define MAP_WRBACK	(0)
21 #define MAP_WRTHROUGH	(0)
22 
23 static inline void *
24 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
25 {
26 	return (void *)((unsigned long)paddr);
27 }
28 
29 /*
30  * Take down a mapping set up by map_physmem().
31  */
32 static inline void unmap_physmem(void *vaddr, unsigned long flags)
33 {
34 
35 }
36 
37 static inline void sync(void)
38 {
39 	/* Not yet implemented */
40 }
41 
42 static inline u8 __raw_readb(const volatile void __iomem *addr)
43 {
44 	u8 b;
45 
46 	__asm__ __volatile__("ldb%U1	%0, %1\n"
47 			     : "=r" (b)
48 			     : "m" (*(volatile u8 __force *)addr)
49 			     : "memory");
50 	return b;
51 }
52 
53 static inline u16 __raw_readw(const volatile void __iomem *addr)
54 {
55 	u16 s;
56 
57 	__asm__ __volatile__("ldw%U1	%0, %1\n"
58 			     : "=r" (s)
59 			     : "m" (*(volatile u16 __force *)addr)
60 			     : "memory");
61 	return s;
62 }
63 
64 static inline u32 __raw_readl(const volatile void __iomem *addr)
65 {
66 	u32 w;
67 
68 	__asm__ __volatile__("ld%U1	%0, %1\n"
69 			     : "=r" (w)
70 			     : "m" (*(volatile u32 __force *)addr)
71 			     : "memory");
72 	return w;
73 }
74 
75 #define readb __raw_readb
76 
77 static inline u16 readw(const volatile void __iomem *addr)
78 {
79 	return __le16_to_cpu(__raw_readw(addr));
80 }
81 
82 static inline u32 readl(const volatile void __iomem *addr)
83 {
84 	return __le32_to_cpu(__raw_readl(addr));
85 }
86 
87 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
88 {
89 	__asm__ __volatile__("stb%U1	%0, %1\n"
90 			     :
91 			     : "r" (b), "m" (*(volatile u8 __force *)addr)
92 			     : "memory");
93 }
94 
95 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
96 {
97 	__asm__ __volatile__("stw%U1	%0, %1\n"
98 			     :
99 			     : "r" (s), "m" (*(volatile u16 __force *)addr)
100 			     : "memory");
101 }
102 
103 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
104 {
105 	__asm__ __volatile__("st%U1	%0, %1\n"
106 			     :
107 			     : "r" (w), "m" (*(volatile u32 __force *)addr)
108 			     : "memory");
109 }
110 
111 #define writeb __raw_writeb
112 #define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
113 #define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
114 
115 static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
116 {
117 	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
118 			      "sub.f	r2, r2, 1\n"
119 			      "bnz.d	1b\n"
120 			      "stb.ab	r8, [r1, 1]\n"
121 			      :
122 			      : "r" (addr), "r" (data), "r" (bytelen)
123 			      : "r8");
124 	return bytelen;
125 }
126 
127 static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
128 {
129 	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
130 			      "sub.f	r2, r2, 1\n"
131 			      "bnz.d	1b\n"
132 			      "stw.ab	r8, [r1, 2]\n"
133 			      :
134 			      : "r" (addr), "r" (data), "r" (wordlen)
135 			      : "r8");
136 	return wordlen;
137 }
138 
139 static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
140 {
141 	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
142 			      "sub.f	r2, r2, 1\n"
143 			      "bnz.d	1b\n"
144 			      "st.ab	r8, [r1, 4]\n"
145 			      :
146 			      : "r" (addr), "r" (data), "r" (longlen)
147 			      : "r8");
148 	return longlen;
149 }
150 
151 static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
152 {
153 	__asm__ __volatile__ ("1:ldb.ab	r8, [r1, 1]\n"
154 			      "sub.f	r2, r2, 1\n"
155 			      "bnz.d	1b\n"
156 			      "st.di	r8, [r0, 0]\n"
157 			      :
158 			      : "r" (addr), "r" (data), "r" (bytelen)
159 			      : "r8");
160 	return bytelen;
161 }
162 
163 static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
164 {
165 	__asm__ __volatile__ ("1:ldw.ab	r8, [r1, 2]\n"
166 			      "sub.f	r2, r2, 1\n"
167 			      "bnz.d	1b\n"
168 			      "st.ab.di	r8, [r0, 0]\n"
169 			      :
170 			      : "r" (addr), "r" (data), "r" (wordlen)
171 			      : "r8");
172 	return wordlen;
173 }
174 
175 static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
176 {
177 	__asm__ __volatile__ ("1:ld.ab	r8, [r1, 4]\n"
178 			      "sub.f	r2, r2, 1\n"
179 			      "bnz.d	1b\n"
180 			      "st.ab.di	r8, [r0, 0]\n"
181 			      :
182 			      : "r" (addr), "r" (data), "r" (longlen)
183 			      : "r8");
184 	return longlen;
185 }
186 
187 #define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
188 #define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
189 
190 #define out_le32(a, v)	out_arch(l, le32, a, v)
191 #define out_le16(a, v)	out_arch(w, le16, a, v)
192 
193 #define in_le32(a)	in_arch(l, le32, a)
194 #define in_le16(a)	in_arch(w, le16, a)
195 
196 #define out_be32(a, v)	out_arch(l, be32, a, v)
197 #define out_be16(a, v)	out_arch(w, be16, a, v)
198 
199 #define in_be32(a)	in_arch(l, be32, a)
200 #define in_be16(a)	in_arch(w, be16, a)
201 
202 #define out_8(a, v)	__raw_writeb(v, a)
203 #define in_8(a)		__raw_readb(a)
204 
205 /*
206  * Clear and set bits in one shot. These macros can be used to clear and
207  * set multiple bits in a register using a single call. These macros can
208  * also be used to set a multiple-bit bit pattern using a mask, by
209  * specifying the mask in the 'clear' parameter and the new bit pattern
210  * in the 'set' parameter.
211  */
212 
213 #define clrbits(type, addr, clear) \
214 	out_##type((addr), in_##type(addr) & ~(clear))
215 
216 #define setbits(type, addr, set) \
217 	out_##type((addr), in_##type(addr) | (set))
218 
219 #define clrsetbits(type, addr, clear, set) \
220 	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
221 
222 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
223 #define setbits_be32(addr, set) setbits(be32, addr, set)
224 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
225 
226 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
227 #define setbits_le32(addr, set) setbits(le32, addr, set)
228 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
229 
230 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
231 #define setbits_be16(addr, set) setbits(be16, addr, set)
232 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
233 
234 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
235 #define setbits_le16(addr, set) setbits(le16, addr, set)
236 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
237 
238 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
239 #define setbits_8(addr, set) setbits(8, addr, set)
240 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
241 
242 static inline phys_addr_t virt_to_phys(void *vaddr)
243 {
244 	return (phys_addr_t)((unsigned long)vaddr);
245 }
246 
247 #endif	/* __ASM_ARC_IO_H */
248