xref: /openbmc/u-boot/arch/arc/include/asm/io.h (revision d66ff4ba) 
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4  */
5 
6 #ifndef __ASM_ARC_IO_H
7 #define __ASM_ARC_IO_H
8 
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
11 
12 #ifdef __ARCHS__
13 
14 /*
15  * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
16  * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
17  *
18  * Explicit barrier provided by DMB instruction
19  *  - Operand supports fine grained load/store/load+store semantics
20  *  - Ensures that selected memory operation issued before it will complete
21  *    before any subsequent memory operation of same type
22  *  - DMB guarantees SMP as well as local barrier semantics
23  *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
24  *    UP: barrier(), SMP: smp_*mb == *mb)
25  *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
26  *    in the general case. Plus it only provides full barrier.
27  */
28 
29 #define mb()	asm volatile("dmb 3\n" : : : "memory")
30 #define rmb()	asm volatile("dmb 1\n" : : : "memory")
31 #define wmb()	asm volatile("dmb 2\n" : : : "memory")
32 
33 #else
34 
35 /*
36  * ARCompact based cores (ARC700) only have SYNC instruction which is super
37  * heavy weight as it flushes the pipeline as well.
38  * There are no real SMP implementations of such cores.
39  */
40 
41 #define mb()	asm volatile("sync\n" : : : "memory")
42 #endif
43 
44 #ifdef __ARCHS__
45 #define __iormb()		rmb()
46 #define __iowmb()		wmb()
47 #else
48 #define __iormb()		asm volatile("" : : : "memory")
49 #define __iowmb()		asm volatile("" : : : "memory")
50 #endif
51 
52 static inline void sync(void)
53 {
54 	/* Not yet implemented */
55 }
56 
57 static inline u8 __raw_readb(const volatile void __iomem *addr)
58 {
59 	u8 b;
60 
61 	__asm__ __volatile__("ldb%U1	%0, %1\n"
62 			     : "=r" (b)
63 			     : "m" (*(volatile u8 __force *)addr)
64 			     : "memory");
65 	return b;
66 }
67 
68 static inline u16 __raw_readw(const volatile void __iomem *addr)
69 {
70 	u16 s;
71 
72 	__asm__ __volatile__("ldw%U1	%0, %1\n"
73 			     : "=r" (s)
74 			     : "m" (*(volatile u16 __force *)addr)
75 			     : "memory");
76 	return s;
77 }
78 
79 static inline u32 __raw_readl(const volatile void __iomem *addr)
80 {
81 	u32 w;
82 
83 	__asm__ __volatile__("ld%U1	%0, %1\n"
84 			     : "=r" (w)
85 			     : "m" (*(volatile u32 __force *)addr)
86 			     : "memory");
87 	return w;
88 }
89 
90 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
91 {
92 	__asm__ __volatile__("stb%U1	%0, %1\n"
93 			     :
94 			     : "r" (b), "m" (*(volatile u8 __force *)addr)
95 			     : "memory");
96 }
97 
98 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
99 {
100 	__asm__ __volatile__("stw%U1	%0, %1\n"
101 			     :
102 			     : "r" (s), "m" (*(volatile u16 __force *)addr)
103 			     : "memory");
104 }
105 
106 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
107 {
108 	__asm__ __volatile__("st%U1	%0, %1\n"
109 			     :
110 			     : "r" (w), "m" (*(volatile u32 __force *)addr)
111 			     : "memory");
112 }
113 
114 static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
115 {
116 	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
117 			      "sub.f	r2, r2, 1\n"
118 			      "bnz.d	1b\n"
119 			      "stb.ab	r8, [r1, 1]\n"
120 			      :
121 			      : "r" (addr), "r" (data), "r" (bytelen)
122 			      : "r8");
123 	return bytelen;
124 }
125 
126 static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
127 {
128 	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
129 			      "sub.f	r2, r2, 1\n"
130 			      "bnz.d	1b\n"
131 			      "stw.ab	r8, [r1, 2]\n"
132 			      :
133 			      : "r" (addr), "r" (data), "r" (wordlen)
134 			      : "r8");
135 	return wordlen;
136 }
137 
138 static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
139 {
140 	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
141 			      "sub.f	r2, r2, 1\n"
142 			      "bnz.d	1b\n"
143 			      "st.ab	r8, [r1, 4]\n"
144 			      :
145 			      : "r" (addr), "r" (data), "r" (longlen)
146 			      : "r8");
147 	return longlen;
148 }
149 
150 static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
151 {
152 	__asm__ __volatile__ ("1:ldb.ab	r8, [r1, 1]\n"
153 			      "sub.f	r2, r2, 1\n"
154 			      "bnz.d	1b\n"
155 			      "st.di	r8, [r0, 0]\n"
156 			      :
157 			      : "r" (addr), "r" (data), "r" (bytelen)
158 			      : "r8");
159 	return bytelen;
160 }
161 
162 static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
163 {
164 	__asm__ __volatile__ ("1:ldw.ab	r8, [r1, 2]\n"
165 			      "sub.f	r2, r2, 1\n"
166 			      "bnz.d	1b\n"
167 			      "st.ab.di	r8, [r0, 0]\n"
168 			      :
169 			      : "r" (addr), "r" (data), "r" (wordlen)
170 			      : "r8");
171 	return wordlen;
172 }
173 
174 static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
175 {
176 	__asm__ __volatile__ ("1:ld.ab	r8, [r1, 4]\n"
177 			      "sub.f	r2, r2, 1\n"
178 			      "bnz.d	1b\n"
179 			      "st.ab.di	r8, [r0, 0]\n"
180 			      :
181 			      : "r" (addr), "r" (data), "r" (longlen)
182 			      : "r8");
183 	return longlen;
184 }
185 
186 /*
187  * MMIO can also get buffered/optimized in micro-arch, so barriers needed
188  * Based on ARM model for the typical use case
189  *
190  *	<ST [DMA buffer]>
191  *	<writel MMIO "go" reg>
192  *  or:
193  *	<readl MMIO "status" reg>
194  *	<LD [DMA buffer]>
195  *
196  * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
197  */
198 #define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
199 #define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
200 #define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })
201 
202 #define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })
203 #define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })
204 #define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })
205 
206 /*
207  * Relaxed API for drivers which can handle barrier ordering themselves
208  *
209  * Also these are defined to perform little endian accesses.
210  * To provide the typical device register semantics of fixed endian,
211  * swap the byte order for Big Endian
212  *
213  * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
214  */
215 #define readb_relaxed(c)	__raw_readb(c)
216 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
217 					__raw_readw(c)); __r; })
218 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
219 					__raw_readl(c)); __r; })
220 
221 #define writeb_relaxed(v,c)	__raw_writeb(v,c)
222 #define writew_relaxed(v,c)	__raw_writew((__force u16) cpu_to_le16(v),c)
223 #define writel_relaxed(v,c)	__raw_writel((__force u32) cpu_to_le32(v),c)
224 
225 #define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
226 #define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
227 
228 #define out_le32(a, v)	out_arch(l, le32, a, v)
229 #define out_le16(a, v)	out_arch(w, le16, a, v)
230 
231 #define in_le32(a)	in_arch(l, le32, a)
232 #define in_le16(a)	in_arch(w, le16, a)
233 
234 #define out_be32(a, v)	out_arch(l, be32, a, v)
235 #define out_be16(a, v)	out_arch(w, be16, a, v)
236 
237 #define in_be32(a)	in_arch(l, be32, a)
238 #define in_be16(a)	in_arch(w, be16, a)
239 
240 #define out_8(a, v)	__raw_writeb(v, a)
241 #define in_8(a)		__raw_readb(a)
242 
243 /*
244  * Clear and set bits in one shot. These macros can be used to clear and
245  * set multiple bits in a register using a single call. These macros can
246  * also be used to set a multiple-bit bit pattern using a mask, by
247  * specifying the mask in the 'clear' parameter and the new bit pattern
248  * in the 'set' parameter.
249  */
250 
251 #define clrbits(type, addr, clear) \
252 	out_##type((addr), in_##type(addr) & ~(clear))
253 
254 #define setbits(type, addr, set) \
255 	out_##type((addr), in_##type(addr) | (set))
256 
257 #define clrsetbits(type, addr, clear, set) \
258 	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
259 
260 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
261 #define setbits_be32(addr, set) setbits(be32, addr, set)
262 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
263 
264 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
265 #define setbits_le32(addr, set) setbits(le32, addr, set)
266 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
267 
268 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
269 #define setbits_be16(addr, set) setbits(be16, addr, set)
270 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
271 
272 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
273 #define setbits_le16(addr, set) setbits(le16, addr, set)
274 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
275 
276 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
277 #define setbits_8(addr, set) setbits(8, addr, set)
278 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
279 
280 #include <asm-generic/io.h>
281 
282 #endif	/* __ASM_ARC_IO_H */
283