xref: /openbmc/u-boot/arch/arc/include/asm/cache.h (revision ae51b570)
1 /*
2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARC_CACHE_H
8 #define __ASM_ARC_CACHE_H
9 
10 #include <config.h>
11 
12 /*
13  * As of today we may handle any L1 cache line length right in software.
14  * For that essentially cache line length is a variable not constant.
15  * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
16  * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
17  */
18 #define ARCH_DMA_MINALIGN	128
19 
20 #if defined(ARC_MMU_ABSENT)
21 #define CONFIG_ARC_MMU_VER 0
22 #elif defined(CONFIG_ARC_MMU_V2)
23 #define CONFIG_ARC_MMU_VER 2
24 #elif defined(CONFIG_ARC_MMU_V3)
25 #define CONFIG_ARC_MMU_VER 3
26 #elif defined(CONFIG_ARC_MMU_V4)
27 #define CONFIG_ARC_MMU_VER 4
28 #endif
29 
30 #ifndef __ASSEMBLY__
31 
32 void cache_init(void);
33 
34 #endif /* __ASSEMBLY__ */
35 
36 #endif /* __ASM_ARC_CACHE_H */
37