1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARC_ARCREGS_H 8 #define _ASM_ARC_ARCREGS_H 9 10 #include <asm/cache.h> 11 12 /* 13 * ARC architecture has additional address space - auxiliary registers. 14 * These registers are mostly used for configuration purposes. 15 * These registers are not memory mapped and special commands are used for 16 * access: "lr"/"sr". 17 */ 18 19 #define ARC_AUX_IDENTITY 0x04 20 #define ARC_AUX_STATUS32 0x0a 21 22 /* Instruction cache related auxiliary registers */ 23 #define ARC_AUX_IC_IVIC 0x10 24 #define ARC_AUX_IC_CTRL 0x11 25 #define ARC_AUX_IC_IVIL 0x19 26 #if (CONFIG_ARC_MMU_VER == 3) 27 #define ARC_AUX_IC_PTAG 0x1E 28 #endif 29 #define ARC_BCR_IC_BUILD 0x77 30 #define AUX_AUX_CACHE_LIMIT 0x5D 31 #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E 32 33 /* ICCM and DCCM auxiliary registers */ 34 #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ 35 #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ 36 37 /* Timer related auxiliary registers */ 38 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 39 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 40 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 41 42 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 43 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 44 #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 45 46 #define ARC_AUX_INTR_VEC_BASE 0x25 47 48 /* Data cache related auxiliary registers */ 49 #define ARC_AUX_DC_IVDC 0x47 50 #define ARC_AUX_DC_CTRL 0x48 51 52 #define ARC_AUX_DC_IVDL 0x4A 53 #define ARC_AUX_DC_FLSH 0x4B 54 #define ARC_AUX_DC_FLDL 0x4C 55 #if (CONFIG_ARC_MMU_VER == 3) 56 #define ARC_AUX_DC_PTAG 0x5C 57 #endif 58 #define ARC_BCR_DC_BUILD 0x72 59 #define ARC_BCR_SLC 0xce 60 #define ARC_AUX_SLC_CONFIG 0x901 61 #define ARC_AUX_SLC_CTRL 0x903 62 #define ARC_AUX_SLC_FLUSH 0x904 63 #define ARC_AUX_SLC_INVALIDATE 0x905 64 #define ARC_AUX_SLC_IVDL 0x910 65 #define ARC_AUX_SLC_FLDL 0x912 66 #define ARC_BCR_CLUSTER 0xcf 67 68 /* IO coherency related auxiliary registers */ 69 #define ARC_AUX_IO_COH_ENABLE 0x500 70 #define ARC_AUX_IO_COH_PARTIAL 0x501 71 #define ARC_AUX_IO_COH_AP0_BASE 0x508 72 #define ARC_AUX_IO_COH_AP0_SIZE 0x509 73 74 #ifndef __ASSEMBLY__ 75 /* Accessors for auxiliary registers */ 76 #define read_aux_reg(reg) __builtin_arc_lr(reg) 77 78 /* gcc builtin sr needs reg param to be long immediate */ 79 #define write_aux_reg(reg_immed, val) \ 80 __builtin_arc_sr((unsigned int)val, reg_immed) 81 82 /* ARCNUM [15:8] - field to identify each core in a multi-core system */ 83 #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) 84 #endif /* __ASSEMBLY__ */ 85 86 #endif /* _ASM_ARC_ARCREGS_H */ 87