1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef _ASM_ARC_ARCREGS_H 7 #define _ASM_ARC_ARCREGS_H 8 9 #include <asm/cache.h> 10 #include <config.h> 11 12 /* 13 * ARC architecture has additional address space - auxiliary registers. 14 * These registers are mostly used for configuration purposes. 15 * These registers are not memory mapped and special commands are used for 16 * access: "lr"/"sr". 17 */ 18 19 #define ARC_AUX_IDENTITY 0x04 20 #define ARC_AUX_STATUS32 0x0a 21 22 /* STATUS32 Bits Positions */ 23 #define STATUS_AD_BIT 19 /* Enable unaligned access */ 24 25 /* Instruction cache related auxiliary registers */ 26 #define ARC_AUX_IC_IVIC 0x10 27 #define ARC_AUX_IC_CTRL 0x11 28 #define ARC_AUX_IC_IVIL 0x19 29 #if (CONFIG_ARC_MMU_VER == 3) 30 #define ARC_AUX_IC_PTAG 0x1E 31 #endif 32 #define ARC_BCR_IC_BUILD 0x77 33 #define AUX_AUX_CACHE_LIMIT 0x5D 34 #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E 35 36 /* ICCM and DCCM auxiliary registers */ 37 #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ 38 #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ 39 40 /* Timer related auxiliary registers */ 41 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 42 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 43 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 44 45 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 46 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 47 #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 48 49 #define ARC_AUX_INTR_VEC_BASE 0x25 50 51 /* Data cache related auxiliary registers */ 52 #define ARC_AUX_DC_IVDC 0x47 53 #define ARC_AUX_DC_CTRL 0x48 54 55 #define ARC_AUX_DC_IVDL 0x4A 56 #define ARC_AUX_DC_FLSH 0x4B 57 #define ARC_AUX_DC_FLDL 0x4C 58 #if (CONFIG_ARC_MMU_VER == 3) 59 #define ARC_AUX_DC_PTAG 0x5C 60 #endif 61 #define ARC_BCR_DC_BUILD 0x72 62 #define ARC_BCR_SLC 0xce 63 #define ARC_AUX_SLC_CONFIG 0x901 64 #define ARC_AUX_SLC_CTRL 0x903 65 #define ARC_AUX_SLC_FLUSH 0x904 66 #define ARC_AUX_SLC_INVALIDATE 0x905 67 #define ARC_AUX_SLC_IVDL 0x910 68 #define ARC_AUX_SLC_FLDL 0x912 69 #define ARC_AUX_SLC_RGN_START 0x914 70 #define ARC_AUX_SLC_RGN_START1 0x915 71 #define ARC_AUX_SLC_RGN_END 0x916 72 #define ARC_AUX_SLC_RGN_END1 0x917 73 #define ARC_BCR_CLUSTER 0xcf 74 75 /* MMU Management regs */ 76 #define ARC_AUX_MMU_BCR 0x06f 77 78 /* IO coherency related auxiliary registers */ 79 #define ARC_AUX_IO_COH_ENABLE 0x500 80 #define ARC_AUX_IO_COH_PARTIAL 0x501 81 #define ARC_AUX_IO_COH_AP0_BASE 0x508 82 #define ARC_AUX_IO_COH_AP0_SIZE 0x509 83 84 #ifndef __ASSEMBLY__ 85 /* Accessors for auxiliary registers */ 86 #define read_aux_reg(reg) __builtin_arc_lr(reg) 87 88 /* gcc builtin sr needs reg param to be long immediate */ 89 #define write_aux_reg(reg_immed, val) \ 90 __builtin_arc_sr((unsigned int)val, reg_immed) 91 92 /* ARCNUM [15:8] - field to identify each core in a multi-core system */ 93 #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) 94 95 static const inline int is_isa_arcv2(void) 96 { 97 return IS_ENABLED(CONFIG_ISA_ARCV2); 98 } 99 100 static const inline int is_isa_arcompact(void) 101 { 102 return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 103 } 104 #endif /* __ASSEMBLY__ */ 105 106 #endif /* _ASM_ARC_ARCREGS_H */ 107