1288aaacfSAlexey Brodkin /* 2288aaacfSAlexey Brodkin * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 3288aaacfSAlexey Brodkin * 4288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5288aaacfSAlexey Brodkin */ 6288aaacfSAlexey Brodkin 7288aaacfSAlexey Brodkin #ifndef _ASM_ARC_ARCREGS_H 8288aaacfSAlexey Brodkin #define _ASM_ARC_ARCREGS_H 9288aaacfSAlexey Brodkin 10812980bdSAlexey Brodkin #include <asm/cache.h> 11812980bdSAlexey Brodkin 12288aaacfSAlexey Brodkin /* 13288aaacfSAlexey Brodkin * ARC architecture has additional address space - auxiliary registers. 14288aaacfSAlexey Brodkin * These registers are mostly used for configuration purposes. 15288aaacfSAlexey Brodkin * These registers are not memory mapped and special commands are used for 16288aaacfSAlexey Brodkin * access: "lr"/"sr". 17288aaacfSAlexey Brodkin */ 18288aaacfSAlexey Brodkin 19288aaacfSAlexey Brodkin #define ARC_AUX_IDENTITY 0x04 20288aaacfSAlexey Brodkin #define ARC_AUX_STATUS32 0x0a 21288aaacfSAlexey Brodkin 22288aaacfSAlexey Brodkin /* Instruction cache related auxiliary registers */ 23288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIC 0x10 24288aaacfSAlexey Brodkin #define ARC_AUX_IC_CTRL 0x11 25288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIL 0x19 265ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 27288aaacfSAlexey Brodkin #define ARC_AUX_IC_PTAG 0x1E 28288aaacfSAlexey Brodkin #endif 29f8cf3d1eSIgor Guryanov #define ARC_BCR_IC_BUILD 0x77 30288aaacfSAlexey Brodkin 31288aaacfSAlexey Brodkin /* Timer related auxiliary registers */ 32288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 33288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 34288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 35288aaacfSAlexey Brodkin 36*ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 37*ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 38*ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 39*ad9b5f77SVlad Zakharov 40288aaacfSAlexey Brodkin #define ARC_AUX_INTR_VEC_BASE 0x25 41288aaacfSAlexey Brodkin 42288aaacfSAlexey Brodkin /* Data cache related auxiliary registers */ 43288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDC 0x47 44288aaacfSAlexey Brodkin #define ARC_AUX_DC_CTRL 0x48 45288aaacfSAlexey Brodkin 46288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDL 0x4A 47288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLSH 0x4B 48288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLDL 0x4C 495ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 50288aaacfSAlexey Brodkin #define ARC_AUX_DC_PTAG 0x5C 51288aaacfSAlexey Brodkin #endif 52f8cf3d1eSIgor Guryanov #define ARC_BCR_DC_BUILD 0x72 536eb15e50SAlexey Brodkin #define ARC_BCR_SLC 0xce 54ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CONFIG 0x901 55ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CTRL 0x903 566eb15e50SAlexey Brodkin #define ARC_AUX_SLC_FLUSH 0x904 576eb15e50SAlexey Brodkin #define ARC_AUX_SLC_INVALIDATE 0x905 58ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_IVDL 0x910 59ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_FLDL 0x912 60db6ce231SAlexey Brodkin #define ARC_BCR_CLUSTER 0xcf 61db6ce231SAlexey Brodkin 62db6ce231SAlexey Brodkin /* IO coherency related auxiliary registers */ 63db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_ENABLE 0x500 64db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_PARTIAL 0x501 65db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_BASE 0x508 66db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_SIZE 0x509 67288aaacfSAlexey Brodkin 68288aaacfSAlexey Brodkin #ifndef __ASSEMBLY__ 69288aaacfSAlexey Brodkin /* Accessors for auxiliary registers */ 70288aaacfSAlexey Brodkin #define read_aux_reg(reg) __builtin_arc_lr(reg) 71288aaacfSAlexey Brodkin 72288aaacfSAlexey Brodkin /* gcc builtin sr needs reg param to be long immediate */ 73288aaacfSAlexey Brodkin #define write_aux_reg(reg_immed, val) \ 74288aaacfSAlexey Brodkin __builtin_arc_sr((unsigned int)val, reg_immed) 75288aaacfSAlexey Brodkin #endif /* __ASSEMBLY__ */ 76288aaacfSAlexey Brodkin 77288aaacfSAlexey Brodkin #endif /* _ASM_ARC_ARCREGS_H */ 78