1288aaacfSAlexey Brodkin /* 2288aaacfSAlexey Brodkin * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 3288aaacfSAlexey Brodkin * 4288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5288aaacfSAlexey Brodkin */ 6288aaacfSAlexey Brodkin 7288aaacfSAlexey Brodkin #ifndef _ASM_ARC_ARCREGS_H 8288aaacfSAlexey Brodkin #define _ASM_ARC_ARCREGS_H 9288aaacfSAlexey Brodkin 10*812980bdSAlexey Brodkin #include <asm/cache.h> 11*812980bdSAlexey Brodkin 12288aaacfSAlexey Brodkin /* 13288aaacfSAlexey Brodkin * ARC architecture has additional address space - auxiliary registers. 14288aaacfSAlexey Brodkin * These registers are mostly used for configuration purposes. 15288aaacfSAlexey Brodkin * These registers are not memory mapped and special commands are used for 16288aaacfSAlexey Brodkin * access: "lr"/"sr". 17288aaacfSAlexey Brodkin */ 18288aaacfSAlexey Brodkin 19288aaacfSAlexey Brodkin #define ARC_AUX_IDENTITY 0x04 20288aaacfSAlexey Brodkin #define ARC_AUX_STATUS32 0x0a 21288aaacfSAlexey Brodkin 22288aaacfSAlexey Brodkin /* Instruction cache related auxiliary registers */ 23288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIC 0x10 24288aaacfSAlexey Brodkin #define ARC_AUX_IC_CTRL 0x11 25288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIL 0x19 26288aaacfSAlexey Brodkin #if (CONFIG_ARC_MMU_VER > 2) 27288aaacfSAlexey Brodkin #define ARC_AUX_IC_PTAG 0x1E 28288aaacfSAlexey Brodkin #endif 29f8cf3d1eSIgor Guryanov #define ARC_BCR_IC_BUILD 0x77 30288aaacfSAlexey Brodkin 31288aaacfSAlexey Brodkin /* Timer related auxiliary registers */ 32288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 33288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 34288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 35288aaacfSAlexey Brodkin 36288aaacfSAlexey Brodkin #define ARC_AUX_INTR_VEC_BASE 0x25 37288aaacfSAlexey Brodkin 38288aaacfSAlexey Brodkin /* Data cache related auxiliary registers */ 39288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDC 0x47 40288aaacfSAlexey Brodkin #define ARC_AUX_DC_CTRL 0x48 41288aaacfSAlexey Brodkin 42288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDL 0x4A 43288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLSH 0x4B 44288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLDL 0x4C 45288aaacfSAlexey Brodkin #if (CONFIG_ARC_MMU_VER > 2) 46288aaacfSAlexey Brodkin #define ARC_AUX_DC_PTAG 0x5C 47288aaacfSAlexey Brodkin #endif 48f8cf3d1eSIgor Guryanov #define ARC_BCR_DC_BUILD 0x72 49288aaacfSAlexey Brodkin 50288aaacfSAlexey Brodkin #ifndef __ASSEMBLY__ 51288aaacfSAlexey Brodkin /* Accessors for auxiliary registers */ 52288aaacfSAlexey Brodkin #define read_aux_reg(reg) __builtin_arc_lr(reg) 53288aaacfSAlexey Brodkin 54288aaacfSAlexey Brodkin /* gcc builtin sr needs reg param to be long immediate */ 55288aaacfSAlexey Brodkin #define write_aux_reg(reg_immed, val) \ 56288aaacfSAlexey Brodkin __builtin_arc_sr((unsigned int)val, reg_immed) 57288aaacfSAlexey Brodkin #endif /* __ASSEMBLY__ */ 58288aaacfSAlexey Brodkin 59288aaacfSAlexey Brodkin #endif /* _ASM_ARC_ARCREGS_H */ 60