1288aaacfSAlexey Brodkin /* 2288aaacfSAlexey Brodkin * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 3288aaacfSAlexey Brodkin * 4288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5288aaacfSAlexey Brodkin */ 6288aaacfSAlexey Brodkin 7288aaacfSAlexey Brodkin #ifndef _ASM_ARC_ARCREGS_H 8288aaacfSAlexey Brodkin #define _ASM_ARC_ARCREGS_H 9288aaacfSAlexey Brodkin 10812980bdSAlexey Brodkin #include <asm/cache.h> 11*5e0c68edSEugeniy Paltsev #include <config.h> 12812980bdSAlexey Brodkin 13288aaacfSAlexey Brodkin /* 14288aaacfSAlexey Brodkin * ARC architecture has additional address space - auxiliary registers. 15288aaacfSAlexey Brodkin * These registers are mostly used for configuration purposes. 16288aaacfSAlexey Brodkin * These registers are not memory mapped and special commands are used for 17288aaacfSAlexey Brodkin * access: "lr"/"sr". 18288aaacfSAlexey Brodkin */ 19288aaacfSAlexey Brodkin 20288aaacfSAlexey Brodkin #define ARC_AUX_IDENTITY 0x04 21288aaacfSAlexey Brodkin #define ARC_AUX_STATUS32 0x0a 22288aaacfSAlexey Brodkin 23288aaacfSAlexey Brodkin /* Instruction cache related auxiliary registers */ 24288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIC 0x10 25288aaacfSAlexey Brodkin #define ARC_AUX_IC_CTRL 0x11 26288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIL 0x19 275ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 28288aaacfSAlexey Brodkin #define ARC_AUX_IC_PTAG 0x1E 29288aaacfSAlexey Brodkin #endif 30f8cf3d1eSIgor Guryanov #define ARC_BCR_IC_BUILD 0x77 3164f47426SEugeniy Paltsev #define AUX_AUX_CACHE_LIMIT 0x5D 3264f47426SEugeniy Paltsev #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E 3364f47426SEugeniy Paltsev 3464f47426SEugeniy Paltsev /* ICCM and DCCM auxiliary registers */ 3564f47426SEugeniy Paltsev #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ 3664f47426SEugeniy Paltsev #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ 37288aaacfSAlexey Brodkin 38288aaacfSAlexey Brodkin /* Timer related auxiliary registers */ 39288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 40288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 41288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 42288aaacfSAlexey Brodkin 43ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 44ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 45ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 46ad9b5f77SVlad Zakharov 47288aaacfSAlexey Brodkin #define ARC_AUX_INTR_VEC_BASE 0x25 48288aaacfSAlexey Brodkin 49288aaacfSAlexey Brodkin /* Data cache related auxiliary registers */ 50288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDC 0x47 51288aaacfSAlexey Brodkin #define ARC_AUX_DC_CTRL 0x48 52288aaacfSAlexey Brodkin 53288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDL 0x4A 54288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLSH 0x4B 55288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLDL 0x4C 565ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 57288aaacfSAlexey Brodkin #define ARC_AUX_DC_PTAG 0x5C 58288aaacfSAlexey Brodkin #endif 59f8cf3d1eSIgor Guryanov #define ARC_BCR_DC_BUILD 0x72 606eb15e50SAlexey Brodkin #define ARC_BCR_SLC 0xce 61ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CONFIG 0x901 62ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CTRL 0x903 636eb15e50SAlexey Brodkin #define ARC_AUX_SLC_FLUSH 0x904 646eb15e50SAlexey Brodkin #define ARC_AUX_SLC_INVALIDATE 0x905 65ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_IVDL 0x910 66ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_FLDL 0x912 6741cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_START 0x914 6841cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_START1 0x915 6941cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_END 0x916 7041cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_END1 0x917 71db6ce231SAlexey Brodkin #define ARC_BCR_CLUSTER 0xcf 72db6ce231SAlexey Brodkin 7341cada4dSEugeniy Paltsev /* MMU Management regs */ 7441cada4dSEugeniy Paltsev #define ARC_AUX_MMU_BCR 0x06f 7541cada4dSEugeniy Paltsev 76db6ce231SAlexey Brodkin /* IO coherency related auxiliary registers */ 77db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_ENABLE 0x500 78db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_PARTIAL 0x501 79db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_BASE 0x508 80db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_SIZE 0x509 81288aaacfSAlexey Brodkin 82288aaacfSAlexey Brodkin #ifndef __ASSEMBLY__ 83288aaacfSAlexey Brodkin /* Accessors for auxiliary registers */ 84288aaacfSAlexey Brodkin #define read_aux_reg(reg) __builtin_arc_lr(reg) 85288aaacfSAlexey Brodkin 86288aaacfSAlexey Brodkin /* gcc builtin sr needs reg param to be long immediate */ 87288aaacfSAlexey Brodkin #define write_aux_reg(reg_immed, val) \ 88288aaacfSAlexey Brodkin __builtin_arc_sr((unsigned int)val, reg_immed) 89e59c3797SEugeniy Paltsev 90e59c3797SEugeniy Paltsev /* ARCNUM [15:8] - field to identify each core in a multi-core system */ 91e59c3797SEugeniy Paltsev #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) 92*5e0c68edSEugeniy Paltsev 93*5e0c68edSEugeniy Paltsev static const inline int is_isa_arcv2(void) 94*5e0c68edSEugeniy Paltsev { 95*5e0c68edSEugeniy Paltsev return IS_ENABLED(CONFIG_ISA_ARCV2); 96*5e0c68edSEugeniy Paltsev } 97*5e0c68edSEugeniy Paltsev 98*5e0c68edSEugeniy Paltsev static const inline int is_isa_arcompact(void) 99*5e0c68edSEugeniy Paltsev { 100*5e0c68edSEugeniy Paltsev return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 101*5e0c68edSEugeniy Paltsev } 102288aaacfSAlexey Brodkin #endif /* __ASSEMBLY__ */ 103288aaacfSAlexey Brodkin 104288aaacfSAlexey Brodkin #endif /* _ASM_ARC_ARCREGS_H */ 105